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Participant idogan
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7,647 Views
Registered: ‎03-09-2016

zynq and marvell dsa 88e6352 integration, device tree

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hi,

 

we have two custom boards that both based on zynq7045 SoC and petalinux is v2015.2.1. We have been trying to up ethernet solution for those zynq boards.

 

One board has two marvell PHYs which are connected to PS MIOs (gem0, gem1) and shared SMI bus (MDC, MDIO). After some search on webs and device tree modifications, we have succeeded to use dual ethernet for this board.

 

Other board has two marvell ethernet switches (88e6352), one is connected to MIO and other is EMIO used with gmii2rgmii ip core. They have seperate SMI bus (MDC, MDIO). However, we have failed to use them, petalinux can not find the switches. And while we are trying to test different configs on device tree configs for them, we have investigated to MDIO,MDC pins via oscilloscope, and we did not see any activity on those pins. It seems that petalinux could not probe the mdio. Finally, we are not sure that our device tree configuration is  suitable or not for marvell dsa (switch 88e6352). And, we also could not find so much informaton about switch-based device tree configuration.

 

Please help about for correct device tree configurations for marvell dsa switches 88e6352 considering our petalinux version which is 2015.2.1. (we have selected the 88e6352 within the petalinux config -c kernel). Is this separate MDIO bus for two zynq ethernet problem?

 

The original petalinux device tree config which is generated after petalinux-build is included.

thanks,

Best Regards,

 

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Participant idogan
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11,155 Views
Registered: ‎03-09-2016

Re: zynq and marvell dsa 88e6352 integration, device tree

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Hi,

 

zynq and marvell 88e6352 ethernet switch integration is completed fully with some problems and their solutiıons and workarounds. . Below you can find the steps for GEM0 and GEM1 integration with their switches;

 

********************************************

Our board setup:

|————————————————————|              |——————————————————————————————————————————|
|     e000b000, GEM0—|———— RGMII ———|—port5 (0x15,act as MAC)        port0 —— PHY0
| Zynq-7045          |              |    mv88e6352 (switch1@addr=2)  ...       |
|     e000c000, GEM1 |———|          | port6 (disabled)               port3 —— PHY3(port4 is not used)
|————————————————————|   |          |—————————————————————————————————————————|

                                                  |

                                                  |

                                                  |          |——————————————————————————————————————————|
                         — RGMII ———|—port5 (0x15,act as MAC)        port0 —— PHY0
                                    |    mv88e6352 (switch2@addr=4)  ...       |
                                    | port6 (disabled)               port3 —— PHY3(port4 is not used)
                                    |—————————————————————————————————————————|

 

 

      * GEM0 is connected to the switch1 with RGMII-MIO signals. GEM0 controls the switch1 over GEM0 MDIO bus via MIO pins. Switch1 addres is 2.
      * GEM1 is connected to the switch2 with RGMII-EMIO signals. In order to do that, GMII2RGMII ip core v4.0 inside the PL side of the zynq is used between GEM1 and the switch2(not shown above graph but there is). GEM1 controls the switch2 over GEM1 MDIO bus via EMIO pins. 
Switch1 addres is 4.

      * That is, GEM0 and GEM1 has separate MDIO buses, this is not shared MDIO design.

      * Our aim is to establish fixed 1000mbps link between port5 of the switches and GEMs of the zynq.

      * Port5 of the switch is not a PHY, it is a MAC. That is, this is a MAC-to-MAC(PHYless) link between GEMs and port5 of the switches over RGMII interface.

      * Port4 of the switches are not used, so they are disabled.

      * Port0-to-Port3 of the switches have internal PHYs. Those are the ethernet interfaces to the outside.

 

Solution Steps:

 

1)  Vivado 2017.2 and Petalinux 2017.2 is installed.

 

2)  DSA/switch and GMII2RGMII related kernel configurations, given below, are enabled from the petalinux-config -c kernel;

 

      * Switch (and switch-ish) device support @ Networking support->Networking options
      * Distributed Switch Architecture @ Networking support->Networking options
      * Distributed Switch Architecture HWMON Support @ Networking support->Networking options->Distributed Switch Architecture  (actually this is optional feature to get such as temp monitoring from the switch device)
      * Marvell 88E6xxx Ethernet switch fabric support @ Device Drivers->Network device support->Distributed Switch Architecture drivers
      * Switch Global 2 Registers support @ Device Drivers->Network device support->Distributed Switch Architecture drivers->Marvell 88E6xxx Ethernet switch fabric support
      * Marvell devices @ Device Drivers->Network device support-> Ethernet driver support
      * Marvell MDIO interface support @ Device Drivers->Network device support-> Ethernet driver support->Marvell devices
      * MDIO Bus/PHY emulation with fixed speed/link PHYs @ Device Drivers->Network device support->PHY Device support and infrastructure

      * Xilinx GMII2RGMII converter driver @ Device Drivers->Network device support->PHY Device support and infrastructure

 

Last one is required for the xilinx gmii2rgmii ip core.

 

3)  MACB driver patch is applied according to the this link https://www.origin.xilinx.com/support/answers/69132.html

 

4)  Device tree modification is made on system-user.dtsi (withinproject-spec/meta-user/recipes-bsp/device-tree/files), given below and attached also;

 

/include/ "system-conf.dtsi"
/ {
        newmdio0: mdio0 {
            compatible = "cdns,macb-mdio";
            reg = <0xe000b000 0x1000>;
            clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
            clock-names = "pclk", "hclk", "tx_clk";
                #address-cells = <1>;
                #size-cells = <0>;
        };

        newmdio1: mdio1 {
            compatible = "cdns,macb-mdio";
            reg = <0xe000c000 0x1000>;
            clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
            clock-names = "pclk", "hclk", "tx_clk";
                #address-cells = <1>;
                #size-cells = <0>;
        };
};

/delete-node/ &ps7_ethernet_1_mdio;

&newmdio0 {
    #address-cells = <1>;
    #size-cells = <0>;

    switch0: switch0@2 {
        compatible = "marvell,mv88e6085";
        #address-cells = <1>;
        #size-cells = <0>;
        reg = <2>;

        dsa,member = <0 0>;

        ports {
            #address-cells = <1>;
            #size-cells = <0>;
            port@0 {
                reg = <0>;
                label = "lan0";
            };

            port@1 {
                reg = <1>;
                label = "lan1";
            };

            port@2 {
                reg = <2>;
                label = "lan2";
            };

            port@3 {
                reg = <3>;
                label = "lan3";
            };

            switch0phy5: port@5 {
                reg = <5>;
                label = "cpu";
                ethernet = <&gem0>;
                phy-mode = "rgmii-id";
                fixed-link {
                    speed = <1000>;
                    full-duplex;
                 };
            };
        };
    };
};

&gem0 {
    local-mac-address = [00 0a 35 00 1e 53];
    phy-handle = <&switch0phy5>;
};

&newmdio1 {
    #address-cells = <1>;
    #size-cells = <0>;

    switch1: switch1@4 {
        compatible = "marvell,mv88e6085";
        #address-cells = <1>;
        #size-cells = <0>;
        reg = <4>;

        dsa,member = <1 0>;

        ports {
            #address-cells = <1>;
            #size-cells = <0>;
            port@0 {
                reg = <0>;
                label = "lan4";
            };

            port@1 {
                reg = <1>;
                label = "lan5";
            };

            port@2 {
                reg = <2>;
                label = "lan6";
            };

            port@3 {
                reg = <3>;
                label = "lan7";
            };

            switch1phy5: port@5 {
                reg = <5>;
                label = "cpu";
                ethernet = <&gem1>;
                phy-mode = "rgmii-id";
                fixed-link {
                    speed = <1000>;
                    full-duplex;
                 };
            };
        };
    };

    gmiitorgmii0: gmiitorgmii@8 {
        compatible = "xlnx,gmii-to-rgmii-1.0";
        reg = <8>;
    };
};

&gem1 {
    local-mac-address = [00 0a 35 00 1e 55];
    gmii2rgmii-phy-handle = <&gmiitorgmii0>;
    phy-handle = <&switch1phy5>;        
};

&qspi {
    u-boot,dm-pre-reloc;
    #address-cells = <1>;
    #size-cells = <0>;
    flash0: flash@0 {
        compatible = "spansion,s25fl512s";
        reg = <0x0>;
        #address-cells = <1>;
        #size-cells = <1>;
        spi-max-frequency = <50000000>;
        partition@0x00000000 {
            label = "boot";
            reg = <0x00000000 0x00d00000>;
        };
        partition@0x00d00000 {
            label = "bootenv";
            reg = <0x00d00000 0x00040000>;
        };
        partition@0x00d40000 {
            label = "kernel";
            reg = <0x00d40000 0x00a80000>;
        };
        partition@0x017c0000 {
            label = "spare";
            reg = <0x017c0000 0x00000000>;
        };
    };
};

 

5) The critical point: Because the connection between zynq and port5 of the switch is rgmii-id, there should be delay between data and clock signals. In order to that, related register bits should be set on switch 88e6352 so that switch 88e6352 can apply internally this delay.

Before this was done manually using mii command at u-boot stage(mii write 0x15 0x01 0xC003), because the kernel could not set fixed-link port5 register for enable TX and RX clk delay. The reason of this analyzed and found the problem as;

 

       * There is a function for the fixed-link port settings of the switches called "mv88e6xxx_adjust_link()" within the "chip.c" (...build/tmp/work-shared/plnx_arm/kernel-source/drivers/net/dsa/mv88e6xxx/chip.c).
       * Within this "mv88e6xxx_adjust_link()" function, in order to be set fixed-link port register for TX/RX clk delays, "phydev->interface" value should come to here correctly.
       * By putting printk, I realized that phydev->interface value is "NA" (val = 0), therefore the TX/RX clk delay bits are not set.
       * "phydev->interface" value is set within dsa_cpu_dsa_setup() function within "dsa.c" by calling "of_get_phy_mode()" func. from the "of_net.c".
       * "of_get_phy_mode()" func. from the "of_net.c" looks for "phy-mode" string of the device node.
       * Since previously there was not given "phy-mode" property within the port5 node of the switch, "phy-mode" was became "NA".

 

Solution:

       * By putting phy-mode = "rgmii-id" into the port5 of the switch1 and switch2 in the device tree, TX and RX clk delay bits are set correctly.
       * After that, GEM0 ping successfully with PC but GEM1 still could not.
       * GEM1 problem and its workaround is related about gmii2rgmii driver explained in below.

 

6) GEM1 problem related about kernel panic which result from the xilinx gmii2rgmii driver, and also gmii2rgmii speed could not be set 1000mbps, it was always 10mbps. Since switch port5 fixed link speed is 1000mbps, but gmii2rgmii speed is 10mbps, GEM1 could not ping with PC.

 

       * When the "phy-handle" property was put into the gmii2rgmii node in device tree, kernel panic was occured at the "memcpy" within "xgmiitorgmii_probe()" function in the xilinx_gmii2rgmii.c
       * In order to prevent it, "phy-handle" property is moved into the gem1 node in the device tree.
       * This time, xgmiitorgmii_probe() return with "Couldn't parse phy-handle" error. (dev_err(dev, "Couldn't parse phy-handle\n")). As a result of that, XILINX_GMII2RGMII_REG could not set with the speed value of MCR_SPEED1000.
       * Before the workaround, I had to use mii command at u-boot stage in order to set 1000mbps into the XILINX_GMII2RGMII_REG. (mii write 0x8 0x10 0x0040)

 

Workaround:

       * By putting  "phy-handle" property into the gem1 node in the device tree,  kernel panic is prevented, but xgmiitorgmii_probe() return with error "Couldn't parse phy-handle".
       * By adding "mdiobus_write()" function into the xgmiitorgmii_probe, before "Couldn't parse phy-handle" error return, XILINX_GMII2RGMII_REG is forced to 1000mbps.
       * In order to do it, a patch file is generated. You can find it attached.
       * Of course, this is not a solution but a workaround.
       * After that, GEM1 also ping successfully with PC.

 

7) After login, ifconfig -a lists all eth0, eth1 and lan0-to-lan7 interfaces. After that, it is required to up eth1, e.g. "ifconfig eth1 up" Then, It is enough to set ip addresses for lan interfaces; e.g. "ifconfig lan0 192.168.0.20",  "ifconfig lan4 192.168.4.24", etc... ping is made successfully between zynq and those lan interfaces.

********************************************

 

Now, GEM0 and GEM1 ping is OK with PC by doing above steps. You can find the patch for the xilinx_gmii2rgmii.c, device tree and console output.

 

thanks,

6 Replies
Participant idogan
Participant
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Registered: ‎03-09-2016

Re: zynq and marvell dsa 88e6352 integration, device tree

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this is for additional information for previous post:

* ethernet switches PORT5 are connected to MIO RGMII and EMIO RGMII. MIO connected switch device address is, which is set by some resistors, 0x02 and EMIO connected switch device address is, which is set by some resistors, 0x04.

 

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Participant idogan
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Registered: ‎03-09-2016

Re: zynq and marvell dsa 88e6352 integration, device tree

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this is the update information about our progress on this thread and current problem about using marvell 88e6352 using with zynq7000 petalinux 2015.2.1 (kernel version 3.19):

 

1) I have disabled the ENET1(gem1), which is connected to EMIO, from the Vivado. That is, currently only gem0(ENET0) is enabled from the Vivado, its rgmii pins are on MIO.

 

2) I changed the address of the 88e6352 to 0. 88e6352 is now in single-chip addresing mode in which all device registers are accessed directly.

 

3) I changed only "system-top.dts" configuration, other files within device tree left as they are. Below, I put the gem0 related part of the zynq-7000.dtsi, pcw.dtsi and modified system-top.dts (note that original system-top.dts file is empty)

 

gem0 related part of the zynq-7000.dtsi:

****************************************************

        gem0: ethernet@e000b000 {
            compatible = "cdns,gem";
            reg = <0xe000b000 0x1000>;
            status = "disabled";
            interrupts = <0 22 4>;
            clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
            clock-names = "pclk", "hclk", "tx_clk";
            #address-cells = <1>;
            #size-cells = <0>;
        };

****************************************************

 

pcw.dts:

****************************************************

/*
 * CAUTION: This file is automatically generated by Xilinx.
 * Version: HSI
 * Today is: Tue Jul 18 09:12:10 2017
*/


/ {
    cpus {
        cpu@0 {
            operating-points = <666666 1000000 333333 1000000>;
        };
    };
};
&gem0 {
    enet-reset = <&gpio0 9 0>;
    phy-mode = "rgmii-id";
    status = "okay";
    xlnx,ptp-enet-clock = <0x69f6bcb>;
    ps7_ethernet_0_mdio: mdio {
        #address-cells = <1>;
        #size-cells = <0>;
    };
};
&gpio0 {
    emio-gpio-width = <64>;
    gpio-mask-high = <0x0>;
    gpio-mask-low = <0x5600>;
};
&i2c0 {
    clock-frequency = <400000>;
    i2c-reset = <&gpio0 46 0>;
    status = "okay";
};
&intc {
    num_cpus = <2>;
    num_interrupts = <96>;
};
&qspi {
    is-dual = <0>;
    num-cs = <1>;
    status = "okay";
};
&sdhci0 {
    clock-frequency = <100000000>;
    status = "okay";
};
&spi0 {
    is-decoded-cs = <0>;
    num-cs = <3>;
    status = "okay";
};
&spi1 {
    is-decoded-cs = <0>;
    num-cs = <3>;
    status = "okay";
};
&uart1 {
    current-speed = <115200>;
    device_type = "serial";
    port-number = <0>;
    status = "okay";
};
&usb0 {
    dr_mode = "host";
    phy_type = "ulpi";
    status = "okay";
    usb-reset = <&gpio0 7 0>;
};
&clkc {
    fclk-enable = <0x7>;
    ps-clk-frequency = <33333333>;
};

****************************************************

 

system-top.dts:

****************************************************

/dts-v1/;
/include/ "system-conf.dtsi"
/ {
       dsa@0 {
                compatible = "marvell,dsa";
                #address-cells = <2>;
            #size-cells = <0>;
                interrupts = <10>;
                dsa,ethernet = <&gem0>;
                dsa,mii-bus = <&ps7_ethernet_0_mdio>;

                switch@0 {
                         #address-cells = <1>;
                         #size-cells = <0>;
                         reg = <0 0>; /* MDIO address 0, switch 0 in tree */
             port@0 {
                    reg = <0>;
                    label = "lan0";
             };                      
             port@1 {
                    reg = <1>;
                    label = "lan1";
             };
             port@2 {
                    reg = <2>;
                    label = "lan2";
             };
             port@3 {
                    reg = <3>;
                    label = "lan3";
             };
             port@4 {
                    reg = <4>;
                    label = "lan4";
             };
             port@5 {
                    reg = <5>;
                    label = "cpu";
                         };
            };
    };
};

&gem0 {
    local-mac-address = [00 0a 35 06 07 08];
    phy-mode = "rgmii-id";
    status = "okay";
    xlnx,ptp-enet-clock = <0x69f6bcb>;
};

****************************************************

 

4) Below petalinux dmesg output is put. Problems are shown as red-bold;

 

 

Booting Linux on physical CPU 0x0
Linux version 3.19.0-xilinx (ibrahimdogan@ID) (gcc version 4.9.1 (Sourcery CodeBench Lite 2014.11-30) ) #15 SMP PREEMPT Fri Jul 21 14:55:55 +03 2017
CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
Machine model: petalinux_out_serial_eth
bootconsole [earlycon0] enabled
cma: Reserved 16 MiB at 0x3f000000
Memory policy: Data cache writealloc
On node 0 totalpages: 262144
free_area_init_node: node 0, pgdat 409fc4c0, node_mem_map 7e7ef000
  Normal zone: 2048 pages used for memmap
  Normal zone: 0 pages reserved
  Normal zone: 262144 pages, LIFO batch:31
PERCPU: Embedded 9 pages/cpu @7e7d0000 s8128 r8192 d20544 u36864
pcpu-alloc: s8128 r8192 d20544 u36864 alloc=9*4096
pcpu-alloc: [0] 0 [0] 1
Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 260096
Kernel command line: console=ttyPS0,115200 earlyprintk
PID hash table entries: 4096 (order: 2, 16384 bytes)
Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
Memory: 1012580K/1048576K available (4713K kernel code, 252K rwdata, 1644K rodata, 3584K init, 207K bss, 19612K reserved, 16384K cma-reserved, 0K highmem)
Virtual kernel memory layout:
    vector  : 0xffff0000 - 0xffff1000   (   4 kB)
    fixmap  : 0xffc00000 - 0xfff00000   (3072 kB)
    vmalloc : 0x80800000 - 0xff000000   (2024 MB)
    lowmem  : 0x40000000 - 0x80000000   (1024 MB)
    pkmap   : 0x3fe00000 - 0x40000000   (   2 MB)
    modules : 0x3f000000 - 0x3fe00000   (  14 MB)
      .text : 0x40008000 - 0x4063d78c   (6358 kB)
      .init : 0x4063e000 - 0x409be000   (3584 kB)
      .data : 0x409be000 - 0x409fd220   ( 253 kB)
       .bss : 0x409fd220 - 0x40a31138   ( 208 kB)
Preemptible hierarchical RCU implementation.
        RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
NR_IRQS:16 nr_irqs:16 16
L2C: platform modifies aux control register: 0x72360000 -> 0x72760000
L2C: DT/platform modifies aux control register: 0x72360000 -> 0x72760000
L2C-310 erratum 769419 enabled
L2C-310 enabling early BRESP for Cortex-A9
L2C-310 full line of zeros enabled for Cortex-A9
L2C-310 ID prefetch enabled, offset 1 lines
L2C-310 dynamic clock gating enabled, standby mode enabled
L2C-310 cache controller enabled, 8 ways, 512 kB
L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x76760001
slcr mapped to 80804000
zynq_clock_init: clkc starts at 80804100
Zynq clock init
sched_clock: 64 bits at 333MHz, resolution 3ns, wraps every 3298534883328ns
timer #0 at 80806000, irq=17
Console: colour dummy device 80x30
Calibrating delay loop... 1332.01 BogoMIPS (lpj=6660096)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
CPU: Testing write buffer coherency: ok
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
Setting up static identity map for 0x476160 - 0x4761b8
CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
Brought up 2 CPUs
SMP: Total of 2 processors activated (2664.03 BogoMIPS).
CPU: All CPU(s) started in SVC mode.
devtmpfs: initialized
VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
NET: Registered protocol family 16
DMA: preallocated 256 KiB pool for atomic coherent allocations
cpuidle: using governor ladder
cpuidle: using governor menu
hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
hw-breakpoint: maximum watchpoint size is 4 bytes.
zynq-ocm f800c000.ocmc: ZYNQ OCM pool: 256 KiB @ 0x80880000
GPIO IRQ not connected
XGpio: /amba_pl/gpio@41200000: registered, base is 1023
XGpio: /amba_pl/gpio@41210000: registered, base is 1022
GPIO IRQ not connected
XGpio: /amba_pl/gpio@41220000: registered, base is 1014
vgaarb: loaded
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
media: Linux media interface: v0.10
Linux video capture interface: v2.00
pps_core: LinuxPPS API ver. 1 registered
pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
PTP clock support registered
EDAC MC: Ver: 3.0.0
Advanced Linux Sound Architecture Driver Initialized.
Switched to clocksource arm_global_timer
NET: Registered protocol family 2
TCP established hash table entries: 8192 (order: 3, 32768 bytes)
TCP bind hash table entries: 8192 (order: 4, 65536 bytes)
TCP: Hash tables configured (established 8192 bind 8192)
TCP: reno registered
UDP hash table entries: 512 (order: 2, 16384 bytes)
UDP-Lite hash table entries: 512 (order: 2, 16384 bytes)
NET: Registered protocol family 1
RPC: Registered named UNIX socket transport module.
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
PCI: CLS 0 bytes, default 64
hw perfevents: enabled with armv7_cortex_a9 PMU driver, 7 counters available
futex hash table entries: 512 (order: 3, 32768 bytes)
jffs2: version 2.2. (NAND) (SUMMARY)  © 2001-2006 Red Hat, Inc.
io scheduler noop registered
io scheduler deadline registered
io scheduler cfq registered (default)
dma-pl330 f8003000.dmac: Loaded driver for PL330 DMAC-241330
dma-pl330 f8003000.dmac:        DBUFF-128x8bytes Num_Chans-8 Num_Peri-4 Num_Events-16
e0001000.serial: ttyPS0 at MMIO 0xe0001000 (irq = 143, base_baud = 3125000) is a xuartps
console [ttyPS0] enabled
bootconsole [earlycon0] disabled
xdevcfg f8007000.devcfg: ioremap 0xf8007000 to 8081a000
[drm] Initialized drm 1.1.0 20060810
brd: module loaded
loop: module loaded
CAN device driver interface
libphy: MACB_mii_bus: probed
mdio_bus e000b000.etherne: /amba/ethernet@e000b000/mdio has invalid PHY address
mdio_bus e000b000.etherne: scan phy mdio at address 0
mdio_bus e000b000.etherne: scan phy mdio at address 1
mdio_bus e000b000.etherne: scan phy mdio at address 2
mdio_bus e000b000.etherne: scan phy mdio at address 3
mdio_bus e000b000.etherne: scan phy mdio at address 4
mdio_bus e000b000.etherne: scan phy mdio at address 5
mdio_bus e000b000.etherne: scan phy mdio at address 6
mdio_bus e000b000.etherne: scan phy mdio at address 7
mdio_bus e000b000.etherne: scan phy mdio at address 8
mdio_bus e000b000.etherne: scan phy mdio at address 9
mdio_bus e000b000.etherne: scan phy mdio at address 10
mdio_bus e000b000.etherne: scan phy mdio at address 11
mdio_bus e000b000.etherne: scan phy mdio at address 12
mdio_bus e000b000.etherne: scan phy mdio at address 13
mdio_bus e000b000.etherne: scan phy mdio at address 14
mdio_bus e000b000.etherne: scan phy mdio at address 15
mdio_bus e000b000.etherne: scan phy mdio at address 16
mdio_bus e000b000.etherne: scan phy mdio at address 17
mdio_bus e000b000.etherne: scan phy mdio at address 18
mdio_bus e000b000.etherne: scan phy mdio at address 19
mdio_bus e000b000.etherne: scan phy mdio at address 20
mdio_bus e000b000.etherne: scan phy mdio at address 21
mdio_bus e000b000.etherne: scan phy mdio at address 22
mdio_bus e000b000.etherne: scan phy mdio at address 23
mdio_bus e000b000.etherne: scan phy mdio at address 24
mdio_bus e000b000.etherne: scan phy mdio at address 25
mdio_bus e000b000.etherne: scan phy mdio at address 26
mdio_bus e000b000.etherne: scan phy mdio at address 27
mdio_bus e000b000.etherne: scan phy mdio at address 28
mdio_bus e000b000.etherne: scan phy mdio at address 29
mdio_bus e000b000.etherne: scan phy mdio at address 30
mdio_bus e000b000.etherne: scan phy mdio at address 31
macb e000b000.ethernet eth0: Cadence GEM rev 0x00020118 at 0xe000b000 irq 147 (00:0a:35:00:1e:53)
macb e000b000.ethernet eth0: attached PHY driver [Generic PHY] (mii_bus:phy_addr=e000b000.etherne:10, irq=-1)
e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
ehci-pci: EHCI PCI platform driver
usbcore: registered new interface driver usb-storage
**************** err=0
**************** i=3
e0002000.usb supply vbus not found, using dummy regulator
platform ci_hdrc.0: Driver ci_hdrc requests probe deferral
mousedev: PS/2 mouse device common for all mice
i2c /dev entries driver
cdns-i2c e0004000.i2c: 400 kHz mmio e0004000 irq 141
zynq-edac f8006000.memory-controller: ecc not enabled
Xilinx Zynq CpuIdle Driver started
Driver 'mmcblk' needs updating - please use bus_type methods
sdhci: Secure Digital Host Controller Interface driver
sdhci: Copyright(c) Pierre Ossman
sdhci-pltfm: SDHCI platform and OF driver helper
sdhci-arasan e0100000.sdhci: No vmmc regulator found
sdhci-arasan e0100000.sdhci: No vqmmc regulator found
mmc0: SDHCI controller on e0100000.sdhci [e0100000.sdhci] using ADMA
ledtrig-cpu: registered to indicate activity on CPUs
usbcore: registered new interface driver usbhid
usbhid: USB HID core driver
TCP: cubic registered
NET: Registered protocol family 17
Distributed Switch Architecture driver version 0.1
dsa: probe of dsa@0 failed with error -22
can: controller area network core (rev 20120528 abi 9)
NET: Registered protocol family 29
can: raw protocol (rev 20120528)
can: broadcast manager protocol (rev 20120528 t)
can: netlink gateway (rev 20130117) max_hops=1
Registering SWP/SWPB emulation handler
platform ci_hdrc.0: Driver ci_hdrc requests probe deferral
/home/ibrahimdogan/C2techProjects/MODEM_SW/ihalos/petalinuxOS/petalinux-v2015.2.1-final/components/linux-kernel/xlnx-3.19/drivers/rtc/hctosys.c: unable to open rtc device (rtc0)
ALSA device list:
  No soundcards found.
Freeing unused kernel memory: 3584K (4063e000 - 409be000)
random: dd urandom read with 0 bits of entropy available
NET: Registered protocol family 10
IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready

 

***************************************************************

 

5) ifconfig output is put below;

 

eth0      Link encap:Ethernet  HWaddr 00:0A:35:00:1E:53  
          UP BROADCAST MULTICAST  MTU:1500  Metric:1
          RX packets:0 errors:0 dropped:0 overruns:0 frame:0
          TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
          collisions:0 txqueuelen:1000
          RX bytes:0 (0.0 B)  TX bytes:0 (0.0 B)
          Interrupt:147 Base address:0xb000

***************************************************************

 

 

Is there anyone can provide some suggestion or solution about this issue related to integration marvell switch, pls??

 

thanks,

 

 

 

 

 

0 Kudos
Participant idogan
Participant
7,497 Views
Registered: ‎03-09-2016

Re: zynq and marvell dsa 88e6352 integration, device tree

Jump to solution

This is next information about thread progress, only reply to me from myself again!! anyway,...

I have added to several debug purposes printk within u-boot and kernel source files (note that petalinux version is 2015.2.1, kernel v3.19)

After some hard efforts, found the problems on both u-boot and kernel sides. Now, from the u-boot side, marvell dsa 88e6352 chip is accessed using mii tools (mii info, mii read, mii write). Buti still kernel side is problem, i have tried lots of alternative device-tree configs, but the petalinux gives same error always.

 

Firstly, i summarized u-boot side;

at u-boot side, realized that MDIO was not working because by somewhat MDIO was not enabled, so zynq could not communicate with dsa-chip with SMI interface.

so, it should be enabled by forcing that within the "/drivers/net/zynq_gem.c" file, manually added to "zynq_gem_init(dev, bis);" function to the at the end of the zynq_gem_initialize() routine just above the line of "return 1;".  this zynq_gem_init() function calls the below line which is required to enable MDIO TX, RX..

 

        /* Setup for Network Control register, MDIO, Rx and Tx enable */
        setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK);

 

Anyway, before doing this change, all mii info, mii read on u-boot returns always zero. Now, as you can see below, we can see the 88e6352 registers and access them;

**************************************************************************

U-Boot-PetaLinux> mii info
PHY 0x10: OUI = 0x3FC00D, Model = 0x12, Rev = 0x01, 1000baseX, HDX
PHY 0x11: OUI = 0x3FC00D, Model = 0x12, Rev = 0x01, 1000baseX, HDX
PHY 0x12: OUI = 0x3FC00D, Model = 0x12, Rev = 0x01, 1000baseX, HDX
PHY 0x13: OUI = 0x3FC00D, Model = 0x12, Rev = 0x01, 1000baseX, HDX
PHY 0x14: OUI = 0x3FC00D, Model = 0x12, Rev = 0x01, 1000baseX, HDX
PHY 0x15: OUI = 0x3FC00D, Model = 0x12, Rev = 0x01, 1000baseX, HDX
PHY 0x16: OUI = 0x3FC00D, Model = 0x12, Rev = 0x01, 1000baseX, HDX
PHY 0x1B: OUI = 0x0000, Model = 0x00, Rev = 0x00,  10baseT, HDX
PHY 0x1D: OUI = 0x0000, Model = 0x00, Rev = 0x00,  10baseT, HDX

U-Boot-PetaLinux> mii read 0x10 0
500F
U-Boot-PetaLinux> mii read 0x15 0
4E07
U-Boot-PetaLinux>

******************************************************************************

 

Secondly, kernel-side,

below related parts of the current console output is given;

lines started with "=========>" are added printk messages. only modification to kernel side is added to printk, not added or deleted any code segments..

anyway, whatever the device tree config, all the time same -22 error occured at the class_find_device() function wihtin "/drivers/base/class.c"

=========> class.c class_find_device() EXIT at return dev without match device!! ERROR!

 

used device-tree as follow, system-top.dts;

/dts-v1/;
/include/ "system-conf.dtsi"
/ {
       dsa@0 {
                compatible = "marvell,dsa";
                #address-cells = <2>;
            #size-cells = <0>;

                interrupts = <10>;
        dsa,ethernet = <&gem0>;
                dsa,mii-bus = <&ps7_ethernet_0_mdio>;

                switch@0{ // also changed @0 to @0x10, nothing changes
                         #address-cells = <1>;
                         #size-cells = <0>;
                         reg = <0x10 0>; /* MDIO address 16, switch 0 in tree */
         port@0 {
                    reg = <0>;
                label = "lan0";
             };                      
         port@1 {
                    reg = <1>;
                label = "lan1";
             };
             port@2 {
                    reg = <2>;
                    label = "lan2";
             };
             port@3 {
                    reg = <3>;
                    label = "lan3";
             };
             port@4 {
                    reg = <4>;
                    label = "lan4";
             };
             port@5 {
                    reg = <5>;
                    label = "cpu";
                         };
            };
    };
};

&gem0 {
    local-mac-address = [00 0a 35 00 1e 59];
};

 

 

 

Starting kernel ...

Booting Linux on physical CPU 0x0
Linux version 3.19.0-xilinx (ibrahimdogan@ID) (gcc version 4.9.1 (Sourcery CodeBench Lite 2014.11-30) ) #59 SMP PREEMPT Sat Jul 22 23:25:09 +03 2017
CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
Machine model: petalinux_out_serial_eth
bootconsole [earlycon0] enabled
cma: Reserved 16 MiB at 0x3f000000
Memory policy: Data cache writealloc
PERCPU: Embedded 9 pages/cpu @7e7d0000 s8128 r8192 d20544 u36864
Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 260096
Kernel command line: console=ttyPS0,115200 earlyprintk
PID hash table entries: 4096 (order: 2, 16384 bytes)
Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
Memory: 1012572K/1048576K available (4713K kernel code, 252K rwdata, 1652K rodata, 3584K init, 207K bss, 19620K reserved, 16384K cma-reserved, 0K highmem)
Virtual kernel memory layout:
    vector  : 0xffff0000 - 0xffff1000   (   4 kB)
    fixmap  : 0xffc00000 - 0xfff00000   (3072 kB)
    vmalloc : 0x80800000 - 0xff000000   (2024 MB)
    lowmem  : 0x40000000 - 0x80000000   (1024 MB)
    pkmap   : 0x3fe00000 - 0x40000000   (   2 MB)
    modules : 0x3f000000 - 0x3fe00000   (  14 MB)
      .text : 0x40008000 - 0x4063f788   (6366 kB)
      .init : 0x40640000 - 0x409c0000   (3584 kB)
      .data : 0x409c0000 - 0x409ff220   ( 253 kB)
       .bss : 0x409ff220 - 0x40a33138   ( 208 kB)
Preemptible hierarchical RCU implementation.
        RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
NR_IRQS:16 nr_irqs:16 16
L2C: platform modifies aux control register: 0x72360000 -> 0x72760000
L2C: DT/platform modifies aux control register: 0x72360000 -> 0x72760000
L2C-310 erratum 769419 enabled
L2C-310 enabling early BRESP for Cortex-A9
L2C-310 full line of zeros enabled for Cortex-A9
L2C-310 ID prefetch enabled, offset 1 lines
L2C-310 dynamic clock gating enabled, standby mode enabled
L2C-310 cache controller enabled, 8 ways, 512 kB
L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x76760001
slcr mapped to 80804000
zynq_clock_init: clkc starts at 80804100
Zynq clock init
sched_clock: 64 bits at 333MHz, resolution 3ns, wraps every 3298534883328ns
timer #0 at 80806000, irq=17
Console: colour dummy device 80x30
Calibrating delay loop... 1332.01 BogoMIPS (lpj=6660096)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
CPU: Testing write buffer coherency: ok
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
Setting up static identity map for 0x476548 - 0x4765a0
CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
Brought up 2 CPUs
SMP: Total of 2 processors activated (2664.03 BogoMIPS).
CPU: All CPU(s) started in SVC mode.
devtmpfs: initialized
VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
NET: Registered protocol family 16
DMA: preallocated 256 KiB pool for atomic coherent allocations
cpuidle: using governor ladder
cpuidle: using governor menu
hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
hw-breakpoint: maximum watchpoint size is 4 bytes.
zynq-ocm f800c000.ocmc: ZYNQ OCM pool: 256 KiB @ 0x80880000
GPIO IRQ not connected
XGpio: /amba_pl/gpio@41200000: registered, base is 1023
XGpio: /amba_pl/gpio@41210000: registered, base is 1022
GPIO IRQ not connected
XGpio: /amba_pl/gpio@41220000: registered, base is 1014
vgaarb: loaded
SCSI subsystem initialized
=========> mdio_bus.c mdio_bus_init() ENTER
=========> mdio_bus.c class_register(&mdio_bus_class) is called ret = 0
=========> mdio_bus.c bus_register(&mdio_bus_type) is called ret = 0
=========> mdio_bus.c mdio_bus_init() EXIT at return ret = 0
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
media: Linux media interface: v0.10
Linux video capture interface: v2.00
pps_core: LinuxPPS API ver. 1 registered
pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
PTP clock support registered
EDAC MC: Ver: 3.0.0
Advanced Linux Sound Architecture Driver Initialized.
Switched to clocksource arm_global_timer
NET: Registered protocol family 2
TCP established hash table entries: 8192 (order: 3, 32768 bytes)
TCP bind hash table entries: 8192 (order: 4, 65536 bytes)
TCP: Hash tables configured (established 8192 bind 8192)
TCP: reno registered
UDP hash table entries: 512 (order: 2, 16384 bytes)
UDP-Lite hash table entries: 512 (order: 2, 16384 bytes)
NET: Registered protocol family 1
RPC: Registered named UNIX socket transport module.
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
hw perfevents: enabled with armv7_cortex_a9 PMU driver, 7 counters available
futex hash table entries: 512 (order: 3, 32768 bytes)
jffs2: version 2.2. (NAND) (SUMMARY)  © 2001-2006 Red Hat, Inc.
io scheduler noop registered
io scheduler deadline registered
io scheduler cfq registered (default)
dma-pl330 f8003000.dmac: Loaded driver for PL330 DMAC-241330
dma-pl330 f8003000.dmac:        DBUFF-128x8bytes Num_Chans-8 Num_Peri-4 Num_Events-16
e0001000.serial: ttyPS0 at MMIO 0xe0001000 (irq = 143, base_baud = 3125000) is a xuartps
�console [ttyPS0] enabled
console [ttyPS0] enabled
bootconsole [earlycon0] disabled
bootconsole [earlycon0] disabled
xdevcfg f8007000.devcfg: ioremap 0xf8007000 to 8081a000
[drm] Initialized drm 1.1.0 20060810
brd: module loaded
loop: module loaded
m25p80 spi32764.0: s25fl512s (65536 Kbytes)
4 ofpart partitions found on MTD device spi32764.0
Creating 4 MTD partitions on "spi32764.0":
0x000000000000-0x000000d00000 : "boot"
0x000000d00000-0x000000d40000 : "bootenv"
0x000000d40000-0x0000017c0000 : "kernel"
0x0000017c0000-0x000004000000 : "spare"
CAN device driver interface
=========> mv88e6xxx.c mv88e6xxx_init() ENTER
=========> mv88e6xxx.c register_switch_driver(&mv88e6352_switch_driver) is called!
=========> mv88e6xxx.c mv88e6xxx_init() EXIT at return 0!
=========> of_mdio.c of_mdiobus_register() ENTER
libphy: MACB_mii_bus: probed
=========> of_mdio.c mdiobus_register(mdio) returned rc OK! = 0
=========> of_mdio.c of_mdiobus_register() next continue to for_each_available_child_of_node(np, child) LOOP
=========> of_mdio.c of_mdio_parse_addr() ENTER
=========> of_mdio.c of_property_read_u32(np, reg, &addr) = ret = -22
mdio_bus e000b000.etherne: /amba/ethernet@e000b000/mdio has invalid PHY address
=========> of_mdio.c of_mdio_parse_addr(&mdio->dev, child) = addr = -22
=========> of_mdio.c be noisy to encourage people to set reg property
mdio_bus e000b000.etherne: scan phy mdio at address 0
=========> of_mdio.c of_mdiobus_register_phy() ENTER
=========> of_mdio.c get_phy_device(mdio, addr, is_c45) is called! addr=0 is_c45=0 phy_id=0
=========> of_mdio.c if (!phy || IS_ERR(phy)) returned ERROR!, 1
=========> of_mdio.c be noisy to encourage people to set reg property
mdio_bus e000b000.etherne: scan phy mdio at address 1
=========> of_mdio.c of_mdiobus_register_phy() ENTER
=========> of_mdio.c get_phy_device(mdio, addr, is_c45) is called! addr=1 is_c45=0 phy_id=0
=========> of_mdio.c if (!phy || IS_ERR(phy)) returned ERROR!, 1
=========> of_mdio.c be noisy to encourage people to set reg property
mdio_bus e000b000.etherne: scan phy mdio at address 2
=========> of_mdio.c of_mdiobus_register_phy() ENTER
=========> of_mdio.c get_phy_device(mdio, addr, is_c45) is called! addr=2 is_c45=0 phy_id=0
=========> of_mdio.c if (!phy || IS_ERR(phy)) returned ERROR!, 1
=========> of_mdio.c be noisy to encourage people to set reg property
mdio_bus e000b000.etherne: scan phy mdio at address 3
=========> of_mdio.c of_mdiobus_register_phy() ENTER
=========> of_mdio.c get_phy_device(mdio, addr, is_c45) is called! addr=3 is_c45=0 phy_id=0
=========> of_mdio.c if (!phy || IS_ERR(phy)) returned ERROR!, 1
=========> of_mdio.c be noisy to encourage people to set reg property
mdio_bus e000b000.etherne: scan phy mdio at address 4
=========> of_mdio.c of_mdiobus_register_phy() ENTER
=========> of_mdio.c get_phy_device(mdio, addr, is_c45) is called! addr=4 is_c45=0 phy_id=0
=========> of_mdio.c if (!phy || IS_ERR(phy)) returned ERROR!, 1
=========> of_mdio.c be noisy to encourage people to set reg property
mdio_bus e000b000.etherne: scan phy mdio at address 5
=========> of_mdio.c of_mdiobus_register_phy() ENTER
=========> of_mdio.c get_phy_device(mdio, addr, is_c45) is called! addr=5 is_c45=0 phy_id=0
=========> of_mdio.c if (!phy || IS_ERR(phy)) returned ERROR!, 1
=========> of_mdio.c be noisy to encourage people to set reg property
mdio_bus e000b000.etherne: scan phy mdio at address 6
=========> of_mdio.c of_mdiobus_register_phy() ENTER
=========> of_mdio.c get_phy_device(mdio, addr, is_c45) is called! addr=6 is_c45=0 phy_id=0
=========> of_mdio.c if (!phy || IS_ERR(phy)) returned ERROR!, 1
=========> of_mdio.c be noisy to encourage people to set reg property
mdio_bus e000b000.etherne: scan phy mdio at address 7
=========> of_mdio.c of_mdiobus_register_phy() ENTER
=========> of_mdio.c get_phy_device(mdio, addr, is_c45) is called! addr=7 is_c45=0 phy_id=0
=========> of_mdio.c if (!phy || IS_ERR(phy)) returned ERROR!, 1
=========> of_mdio.c be noisy to encourage people to set reg property
mdio_bus e000b000.etherne: scan phy mdio at address 8
=========> of_mdio.c of_mdiobus_register_phy() ENTER
=========> of_mdio.c get_phy_device(mdio, addr, is_c45) is called! addr=8 is_c45=0 phy_id=0
=========> of_mdio.c if (!phy || IS_ERR(phy)) returned ERROR!, 1
=========> of_mdio.c be noisy to encourage people to set reg property
mdio_bus e000b000.etherne: scan phy mdio at address 9
=========> of_mdio.c of_mdiobus_register_phy() ENTER
=========> of_mdio.c get_phy_device(mdio, addr, is_c45) is called! addr=9 is_c45=0 phy_id=0
=========> of_mdio.c if (!phy || IS_ERR(phy)) returned ERROR!, 1
=========> of_mdio.c be noisy to encourage people to set reg property
mdio_bus e000b000.etherne: scan phy mdio at address 10
=========> of_mdio.c of_mdiobus_register_phy() ENTER
=========> of_mdio.c get_phy_device(mdio, addr, is_c45) is called! addr=10 is_c45=0 phy_id=0
=========> of_mdio.c if (!phy || IS_ERR(phy)) returned ERROR!, 1
=========> of_mdio.c be noisy to encourage people to set reg property
mdio_bus e000b000.etherne: scan phy mdio at address 11
=========> of_mdio.c of_mdiobus_register_phy() ENTER
=========> of_mdio.c get_phy_device(mdio, addr, is_c45) is called! addr=11 is_c45=0 phy_id=0
=========> of_mdio.c if (!phy || IS_ERR(phy)) returned ERROR!, 1
=========> of_mdio.c be noisy to encourage people to set reg property
mdio_bus e000b000.etherne: scan phy mdio at address 12
=========> of_mdio.c of_mdiobus_register_phy() ENTER
=========> of_mdio.c get_phy_device(mdio, addr, is_c45) is called! addr=12 is_c45=0 phy_id=0
=========> of_mdio.c if (!phy || IS_ERR(phy)) returned ERROR!, 1
=========> of_mdio.c be noisy to encourage people to set reg property
mdio_bus e000b000.etherne: scan phy mdio at address 13
=========> of_mdio.c of_mdiobus_register_phy() ENTER
=========> of_mdio.c get_phy_device(mdio, addr, is_c45) is called! addr=13 is_c45=0 phy_id=0
=========> of_mdio.c if (!phy || IS_ERR(phy)) returned ERROR!, 1
=========> of_mdio.c be noisy to encourage people to set reg property
mdio_bus e000b000.etherne: scan phy mdio at address 14
=========> of_mdio.c of_mdiobus_register_phy() ENTER
=========> of_mdio.c get_phy_device(mdio, addr, is_c45) is called! addr=14 is_c45=0 phy_id=0
=========> of_mdio.c if (!phy || IS_ERR(phy)) returned ERROR!, 1
=========> of_mdio.c be noisy to encourage people to set reg property
mdio_bus e000b000.etherne: scan phy mdio at address 15
=========> of_mdio.c of_mdiobus_register_phy() ENTER
=========> of_mdio.c get_phy_device(mdio, addr, is_c45) is called! addr=15 is_c45=0 phy_id=0
=========> of_mdio.c if (!phy || IS_ERR(phy)) returned ERROR!, 1
=========> of_mdio.c be noisy to encourage people to set reg property
mdio_bus e000b000.etherne: scan phy mdio at address 16
=========> of_mdio.c of_mdiobus_register_phy() ENTER
=========> of_mdio.c get_phy_device(mdio, addr, is_c45) is called! addr=16 is_c45=0 phy_id=0
=========> of_mdio.c if (!phy || IS_ERR(phy)) returned OK!
=========> of_mdio.c phy_device_register(phy) returned OK!
=========> of_mdio.c registered phy mdio at address 16
=========> of_mdio.c of_mdiobus_register_phy() EXIT at return 0!
=========> of_mdio.c be noisy to encourage people to set reg property
mdio_bus e000b000.etherne: scan phy mdio at address 17
=========> of_mdio.c of_mdiobus_register_phy() ENTER
=========> of_mdio.c get_phy_device(mdio, addr, is_c45) is called! addr=17 is_c45=0 phy_id=0
=========> of_mdio.c if (!phy || IS_ERR(phy)) returned OK!
=========> of_mdio.c phy_device_register(phy) returned OK!
=========> of_mdio.c registered phy mdio at address 17
=========> of_mdio.c of_mdiobus_register_phy() EXIT at return 0!
=========> of_mdio.c be noisy to encourage people to set reg property
mdio_bus e000b000.etherne: scan phy mdio at address 18
=========> of_mdio.c of_mdiobus_register_phy() ENTER
=========> of_mdio.c get_phy_device(mdio, addr, is_c45) is called! addr=18 is_c45=0 phy_id=0
=========> of_mdio.c if (!phy || IS_ERR(phy)) returned OK!
=========> of_mdio.c phy_device_register(phy) returned OK!
=========> of_mdio.c registered phy mdio at address 18
=========> of_mdio.c of_mdiobus_register_phy() EXIT at return 0!
=========> of_mdio.c be noisy to encourage people to set reg property
mdio_bus e000b000.etherne: scan phy mdio at address 19
=========> of_mdio.c of_mdiobus_register_phy() ENTER
=========> of_mdio.c get_phy_device(mdio, addr, is_c45) is called! addr=19 is_c45=0 phy_id=0
=========> of_mdio.c if (!phy || IS_ERR(phy)) returned OK!
=========> of_mdio.c phy_device_register(phy) returned OK!
=========> of_mdio.c registered phy mdio at address 19
=========> of_mdio.c of_mdiobus_register_phy() EXIT at return 0!
=========> of_mdio.c be noisy to encourage people to set reg property
mdio_bus e000b000.etherne: scan phy mdio at address 20
=========> of_mdio.c of_mdiobus_register_phy() ENTER
=========> of_mdio.c get_phy_device(mdio, addr, is_c45) is called! addr=20 is_c45=0 phy_id=0
=========> of_mdio.c if (!phy || IS_ERR(phy)) returned OK!
=========> of_mdio.c phy_device_register(phy) returned OK!
=========> of_mdio.c registered phy mdio at address 20
=========> of_mdio.c of_mdiobus_register_phy() EXIT at return 0!
=========> of_mdio.c be noisy to encourage people to set reg property
mdio_bus e000b000.etherne: scan phy mdio at address 21
=========> of_mdio.c of_mdiobus_register_phy() ENTER
=========> of_mdio.c get_phy_device(mdio, addr, is_c45) is called! addr=21 is_c45=0 phy_id=0
=========> of_mdio.c if (!phy || IS_ERR(phy)) returned OK!
=========> of_mdio.c phy_device_register(phy) returned OK!
=========> of_mdio.c registered phy mdio at address 21
=========> of_mdio.c of_mdiobus_register_phy() EXIT at return 0!
=========> of_mdio.c be noisy to encourage people to set reg property
mdio_bus e000b000.etherne: scan phy mdio at address 22
=========> of_mdio.c of_mdiobus_register_phy() ENTER
=========> of_mdio.c get_phy_device(mdio, addr, is_c45) is called! addr=22 is_c45=0 phy_id=0
=========> of_mdio.c if (!phy || IS_ERR(phy)) returned OK!
=========> of_mdio.c phy_device_register(phy) returned OK!
=========> of_mdio.c registered phy mdio at address 22
=========> of_mdio.c of_mdiobus_register_phy() EXIT at return 0!
=========> of_mdio.c be noisy to encourage people to set reg property
mdio_bus e000b000.etherne: scan phy mdio at address 23
=========> of_mdio.c of_mdiobus_register_phy() ENTER
=========> of_mdio.c get_phy_device(mdio, addr, is_c45) is called! addr=23 is_c45=0 phy_id=0
=========> of_mdio.c if (!phy || IS_ERR(phy)) returned ERROR!, 1
=========> of_mdio.c be noisy to encourage people to set reg property
mdio_bus e000b000.etherne: scan phy mdio at address 24
=========> of_mdio.c of_mdiobus_register_phy() ENTER
=========> of_mdio.c get_phy_device(mdio, addr, is_c45) is called! addr=24 is_c45=0 phy_id=0
=========> of_mdio.c if (!phy || IS_ERR(phy)) returned ERROR!, 1
=========> of_mdio.c be noisy to encourage people to set reg property
mdio_bus e000b000.etherne: scan phy mdio at address 25
=========> of_mdio.c of_mdiobus_register_phy() ENTER
=========> of_mdio.c get_phy_device(mdio, addr, is_c45) is called! addr=25 is_c45=0 phy_id=0
=========> of_mdio.c if (!phy || IS_ERR(phy)) returned ERROR!, 1
=========> of_mdio.c be noisy to encourage people to set reg property
mdio_bus e000b000.etherne: scan phy mdio at address 26
=========> of_mdio.c of_mdiobus_register_phy() ENTER
=========> of_mdio.c get_phy_device(mdio, addr, is_c45) is called! addr=26 is_c45=0 phy_id=0
=========> of_mdio.c if (!phy || IS_ERR(phy)) returned ERROR!, 1
=========> of_mdio.c be noisy to encourage people to set reg property
mdio_bus e000b000.etherne: scan phy mdio at address 27
=========> of_mdio.c of_mdiobus_register_phy() ENTER
=========> of_mdio.c get_phy_device(mdio, addr, is_c45) is called! addr=27 is_c45=0 phy_id=0
=========> of_mdio.c if (!phy || IS_ERR(phy)) returned OK!
=========> of_mdio.c phy_device_register(phy) returned OK!
=========> of_mdio.c registered phy mdio at address 27
=========> of_mdio.c of_mdiobus_register_phy() EXIT at return 0!
=========> of_mdio.c be noisy to encourage people to set reg property
mdio_bus e000b000.etherne: scan phy mdio at address 28
=========> of_mdio.c of_mdiobus_register_phy() ENTER
=========> of_mdio.c get_phy_device(mdio, addr, is_c45) is called! addr=28 is_c45=0 phy_id=0
=========> of_mdio.c if (!phy || IS_ERR(phy)) returned ERROR!, 1
=========> of_mdio.c be noisy to encourage people to set reg property
mdio_bus e000b000.etherne: scan phy mdio at address 29
=========> of_mdio.c of_mdiobus_register_phy() ENTER
=========> of_mdio.c get_phy_device(mdio, addr, is_c45) is called! addr=29 is_c45=0 phy_id=0
=========> of_mdio.c if (!phy || IS_ERR(phy)) returned OK!
=========> of_mdio.c phy_device_register(phy) returned OK!
=========> of_mdio.c registered phy mdio at address 29
=========> of_mdio.c of_mdiobus_register_phy() EXIT at return 0!
=========> of_mdio.c be noisy to encourage people to set reg property
mdio_bus e000b000.etherne: scan phy mdio at address 30
=========> of_mdio.c of_mdiobus_register_phy() ENTER
=========> of_mdio.c get_phy_device(mdio, addr, is_c45) is called! addr=30 is_c45=0 phy_id=0
=========> of_mdio.c if (!phy || IS_ERR(phy)) returned ERROR!, 1
=========> of_mdio.c be noisy to encourage people to set reg property
mdio_bus e000b000.etherne: scan phy mdio at address 31
=========> of_mdio.c of_mdiobus_register_phy() ENTER
=========> of_mdio.c get_phy_device(mdio, addr, is_c45) is called! addr=31 is_c45=0 phy_id=0
=========> of_mdio.c if (!phy || IS_ERR(phy)) returned ERROR!, 1
=========> of_mdio.c of_mdiobus_register() EXIT at return 0!
macb e000b000.ethernet eth0: Cadence GEM rev 0x00020118 at 0xe000b000 irq 147 (00:0a:35:00:1e:53)
macb e000b000.ethernet eth0: attached PHY driver [Generic PHY] (mii_bus:phy_addr=e000b000.etherne:10, irq=-1)
e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
ehci-pci: EHCI PCI platform driver
usbcore: registered new interface driver usb-storage
**************** err=0
**************** i=3
e0002000.usb supply vbus not found, using dummy regulator
platform ci_hdrc.0: Driver ci_hdrc requests probe deferral
mousedev: PS/2 mouse device common for all mice
i2c /dev entries driver
cdns-i2c e0004000.i2c: 400 kHz mmio e0004000 irq 141
zynq-edac f8006000.memory-controller: ecc not enabled
Xilinx Zynq CpuIdle Driver started
Driver 'mmcblk' needs updating - please use bus_type methods
sdhci: Secure Digital Host Controller Interface driver
sdhci: Copyright(c) Pierre Ossman
sdhci-pltfm: SDHCI platform and OF driver helper
sdhci-arasan e0100000.sdhci: No vmmc regulator found
sdhci-arasan e0100000.sdhci: No vqmmc regulator found
mmc0: SDHCI controller on e0100000.sdhci [e0100000.sdhci] using ADMA
ledtrig-cpu: registered to indicate activity on CPUs
usbcore: registered new interface driver usbhid
usbhid: USB HID core driver
TCP: cubic registered
NET: Registered protocol family 17
=========> dsa.c dsa_init_module() ENTER
Distributed Switch Architecture driver version 0.1
=========> dsa.c dsa_probe() ENTER
=========> dsa.c if (pdev->dev.of_node) OK!
=========> dsa.c dsa.c dsa_of_probe() ENTER
=========> dsa.c of_parse_phandle(dsa,mii-bus) returned device_node *mdio OK!
=========> mdio_bus.c of_mdio_find_bus() ENTER
=========> mdio_bus.c if (!mdio_bus_np) returned OK!
=========> class.c class_find_device() ENTER
=========> class.c class_find_device() EXIT at return dev without match device!! ERROR!
=========> mdio_bus.c class_find_device() returned ERROR and EXIT at NULL!
=========> dsa.c of_mdio_find_bus(mdio) returned mii_bus *mdio_bus ERROR!,-22
=========> dsa.c dsa_of_probe(pdev) returned ret ERROR! = -22
dsa: probe of dsa@0 failed with error -22
=========> dsa.c dev_add_pack(&dsa_pack_type) is called!
=========> dsa.c dsa_init_module() EXIT at return 0!
can: controller area network core (rev 20120528 abi 9)
NET: Registered protocol family 29
can: raw protocol (rev 20120528)
can: broadcast manager protocol (rev 20120528 t)
can: netlink gateway (rev 20130117) max_hops=1
Registering SWP/SWPB emulation handler
platform ci_hdrc.0: Driver ci_hdrc requests probe deferral
/home/ibrahimdogan/C2techProjects/MODEM_SW/ihalos/petalinuxOS/petalinux-v2015.2.1-final/components/linux-kernel/xlnx-3.19/drivers/rtc/hctosys.c: unable to open rtc dev
ice (rtc0)
ALSA device list:
  No soundcards found.
Freeing unused kernel memory: 3584K (40640000 - 409c0000)
INIT: version 2.88 booting
Creating /dev/flash/* device nodes
random: dd urandom read with 0 bits of entropy available
starting Busybox inet Daemon: inetd... done.
Starting uWeb server:
NET: Registered protocol family 10
update-rc.d: /etc/init.d/run-postinsts exists during rc.d purge (continuing)
 Removing any system startup links for run-postinsts ...
  /etc/rcS.d/S99run-postinsts
INIT: Entering runlevel: 5
Configuring network interfaces... IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
udhcpc (v1.23.1) started
Sending discover...
Sending discover...
Sending discover...
No lease, forking to background
done.

Built with PetaLinux v2015.2.1 (Yocto 1.8) petalinux_out_serial_eth /dev/ttyPS0
petalinux_out_serial_eth login: 
root@petalinux_out_serial_eth:~# ifconfig
eth0      Link encap:Ethernet  HWaddr 00:0A:35:00:1E:53  
          UP BROADCAST MULTICAST  MTU:1500  Metric:1
          RX packets:0 errors:0 dropped:0 overruns:0 frame:0
          TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
          collisions:0 txqueuelen:1000 
          RX bytes:0 (0.0 B)  TX bytes:0 (0.0 B)
          Interrupt:147 Base address:0xb000 

lo        Link encap:Local Loopback  
          inet addr:127.0.0.1  Mask:255.0.0.0
          inet6 addr: ::1/128 Scope:Host
          UP LOOPBACK RUNNING  MTU:65536  Metric:1
          RX packets:0 errors:0 dropped:0 overruns:0 frame:0
          TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
          collisions:0 txqueuelen:0 
          RX bytes:0 (0.0 B)  TX bytes:0 (0.0 B)

root@petalinux_out_serial_eth:~# 

 

I am not so familiar with petalinux kernel, device tree, so is there anyone to be able to make some suggestions???

thanks,

 

 

 

 

 

 

 

0 Kudos
Participant idogan
Participant
7,464 Views
Registered: ‎03-09-2016

Re: zynq and marvell dsa 88e6352 integration, device tree

Jump to solution

Hi,

I switched to Vivado 2016.1 and petalinux 2016.1.

U-boot side is fixed, marvell switch device can be accessed via mii tool without touching uboot source.

Still kernel side, same problem exits; but in different way....normally DSA probe is called and there is no any error seen on the console but, again after putting printks within dsa.c, of_mdio.c and mdio_bus.c, problematic part is shown as;

class_find_device = NULL occurs within  of_mdio_find_bus() function of mdio_bus.c

 

usbcore: registered new interface driver usbhid
usbhid: USB HID core driver
NET: Registered protocol family 17
=========> dsa.c dsa_init_module() ENTER!
=========> dsa.c dsa_probe() ENTER!
Distributed Switch Architecture driver version 0.1
=========> dsa.c dsa_of_probe() ENTER!
=========> dsa.c dsa_of_probe() mdio = of_parse_phandle(dsa,mii-bus)!
=========> mdio_bus.c of_mdio_find_bus() ENTER!
=========> mdio_bus.c if (!mdio_bus_np) = mii_bus pointer = OK!
=========> mdio_bus.c d = class_find_device = NULL EXIT!
=========> dsa.c dsa_probe() ret = dsa_of_probe(&pdev->dev) = -517!
can: controller area network core (rev 20120528 abi 9)
NET: Registered protocol family 29
can: raw protocol (rev 20120528)

 

full console is below;

 

Starting kernel ...

Booting Linux on physical CPU 0x0
Linux version 4.4.0-xilinx (ibrahimdogan@ID) (gcc version 4.9.2 20140904 (prerelease) (crosstool-NG linaro-1.13.1-4.9-2014.09 - Linaro GCC 4.9-2014.09) ) #39 SMP PREE
MPT Tue Jul 25 02:11:15 +03 2017
CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
Machine model: petalinux_out_serial_eth_2016_1
bootconsole [earlycon0] enabled
cma: Reserved 16 MiB at 0x3f000000
Memory policy: Data cache writealloc
PERCPU: Embedded 12 pages/cpu @ef7d2000 s19264 r8192 d21696 u49152
Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 260608
Kernel command line: console=ttyPS0,115200 earlyprintk
PID hash table entries: 4096 (order: 2, 16384 bytes)
Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
Memory: 1013204K/1048576K available (4869K kernel code, 219K rwdata, 1788K rodata, 2692K init, 213K bss, 18988K reserved, 16384K cma-reserved, 245760K highmem)
Virtual kernel memory layout:
    vector  : 0xffff0000 - 0xffff1000   (   4 kB)
    fixmap  : 0xffc00000 - 0xfff00000   (3072 kB)
    vmalloc : 0xf0800000 - 0xff800000   ( 240 MB)
    lowmem  : 0xc0000000 - 0xf0000000   ( 768 MB)
    pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
    modules : 0xbf000000 - 0xbfe00000   (  14 MB)
      .text : 0xc0008000 - 0xc068877c   (6658 kB)
      .init : 0xc0689000 - 0xc092a000   (2692 kB)
      .data : 0xc092a000 - 0xc0960f60   ( 220 kB)
       .bss : 0xc0960f60 - 0xc09965c4   ( 214 kB)
Preemptible hierarchical RCU implementation.
        Build-time adjustment of leaf fanout to 32.
        RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
RCU: Adjusting geometry for rcu_fanout_leaf=32, nr_cpu_ids=2
NR_IRQS:16 nr_irqs:16 16
slcr mapped to f0802000
L2C: platform modifies aux control register: 0x72360000 -> 0x72760000
L2C: DT/platform modifies aux control register: 0x72360000 -> 0x72760000
L2C-310 erratum 769419 enabled
L2C-310 enabling early BRESP for Cortex-A9
L2C-310 full line of zeros enabled for Cortex-A9
L2C-310 ID prefetch enabled, offset 1 lines
L2C-310 dynamic clock gating enabled, standby mode enabled
L2C-310 cache controller enabled, 8 ways, 512 kB
L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x76760001
zynq_clock_init: clkc starts at f0802100
Zynq clock init
sched_clock: 64 bits at 333MHz, resolution 3ns, wraps every 4398046511103ns
clocksource: arm_global_timer: mask: 0xffffffffffffffff max_cycles: 0x4ce07af025, max_idle_ns: 440795209040 ns
clocksource: ttc_clocksource: mask: 0xffff max_cycles: 0xffff, max_idle_ns: 537538477 ns
timer #0 at f080a000, irq=17
Console: colour dummy device 80x30
Calibrating delay loop... 1332.01 BogoMIPS (lpj=6660096)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
CPU: Testing write buffer coherency: ok
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
Setting up static identity map for 0x82c0 - 0x8318
CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
Brought up 2 CPUs
SMP: Total of 2 processors activated (2664.03 BogoMIPS).
CPU: All CPU(s) started in SVC mode.
devtmpfs: initialized
VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
pinctrl core: initialized pinctrl subsystem
NET: Registered protocol family 16
DMA: preallocated 256 KiB pool for atomic coherent allocations
cpuidle: using governor ladder
cpuidle: using governor menu
hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
hw-breakpoint: maximum watchpoint size is 4 bytes.
zynq-ocm f800c000.ocmc: ZYNQ OCM pool: 256 KiB @ 0xf0880000
zynq-pinctrl 700.pinctrl: zynq pinctrl initialized
GPIO IRQ not connected
XGpio: /amba_pl/gpio@41200000: registered, base is 905
XGpio: /amba_pl/gpio@41210000: registered, base is 904
GPIO IRQ not connected
XGpio: /amba_pl/gpio@41220000: registered, base is 896
vgaarb: loaded
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
media: Linux media interface: v0.10
Linux video capture interface: v2.00
pps_core: LinuxPPS API ver. 1 registered
pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
PTP clock support registered
EDAC MC: Ver: 3.0.0
Advanced Linux Sound Architecture Driver Initialized.
clocksource: Switched to clocksource arm_global_timer
NET: Registered protocol family 2
TCP established hash table entries: 8192 (order: 3, 32768 bytes)
TCP bind hash table entries: 8192 (order: 4, 65536 bytes)
TCP: Hash tables configured (established 8192 bind 8192)
UDP hash table entries: 512 (order: 2, 16384 bytes)
UDP-Lite hash table entries: 512 (order: 2, 16384 bytes)
NET: Registered protocol family 1
RPC: Registered named UNIX socket transport module.
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
hw perfevents: enabled with armv7_cortex_a9 PMU driver, 7 counters available
futex hash table entries: 512 (order: 3, 32768 bytes)
jffs2: version 2.2. (NAND) (SUMMARY)  © 2001-2006 Red Hat, Inc.
bounce: pool size: 64 pages
io scheduler noop registered
io scheduler deadline registered
io scheduler cfq registered (default)
dma-pl330 f8003000.dmac: Loaded driver for PL330 DMAC-241330
dma-pl330 f8003000.dmac:        DBUFF-128x8bytes Num_Chans-8 Num_Peri-4 Num_Events-16
e0001000.serial: ttyPS0 at MMIO 0xe0001000 (irq = 144, base_baud = 3125000) is a xuartps
�console [ttyPS0] enabled
console [ttyPS0] enabled
bootconsole [earlycon0] disabled
bootconsole [earlycon0] disabled
xdevcfg f8007000.devcfg: ioremap 0xf8007000 to f087e000
[drm] Initialized drm 1.1.0 20060810
brd: module loaded
loop: module loaded
m25p80 spi0.0: s25fl512s (65536 Kbytes)
4 ofpart partitions found on MTD device spi0.0
Creating 4 MTD partitions on "spi0.0":
0x000000000000-0x000000d00000 : "boot"
0x000000d00000-0x000000d40000 : "bootenv"
0x000000d40000-0x0000017c0000 : "kernel"
0x0000017c0000-0x000004000000 : "spare"
CAN device driver interface
=========> dsa.c register_switch_driver() ENTER!
=========> dsa.c register_switch_driver() mutex_lock(&dsa_switch_drivers_mutex)
=========> dsa.c register_switch_driver() mutex_unlock(&dsa_switch_drivers_mutex)
=========> dsa.c register_switch_driver() EXIT!
=========> of_mdio.c of_mdiobus_register() ENTER!
libphy: MACB_mii_bus: probed
=========> of_mdio.c Register the MDIO bus!
mdio_bus e000b000.etherne: /amba/ethernet@e000b000/mdio has invalid PHY address
=========> of_mdio.c Loop over the child nodes and register a phy_device for each one, addr = -22!
mdio_bus e000b000.etherne: scan phy mdio at address 0
=========> of_mdio.c of_mdiobus_register_phy() ENTER!
mdio_bus e000b000.etherne: scan phy mdio at address 1
=========> of_mdio.c of_mdiobus_register_phy() ENTER!
mdio_bus e000b000.etherne: scan phy mdio at address 2
=========> of_mdio.c of_mdiobus_register_phy() ENTER!
mdio_bus e000b000.etherne: scan phy mdio at address 3
=========> of_mdio.c of_mdiobus_register_phy() ENTER!
mdio_bus e000b000.etherne: scan phy mdio at address 4
=========> of_mdio.c of_mdiobus_register_phy() ENTER!
mdio_bus e000b000.etherne: scan phy mdio at address 5
=========> of_mdio.c of_mdiobus_register_phy() ENTER!
mdio_bus e000b000.etherne: scan phy mdio at address 6
=========> of_mdio.c of_mdiobus_register_phy() ENTER!
mdio_bus e000b000.etherne: scan phy mdio at address 7
=========> of_mdio.c of_mdiobus_register_phy() ENTER!
mdio_bus e000b000.etherne: scan phy mdio at address 8
=========> of_mdio.c of_mdiobus_register_phy() ENTER!
mdio_bus e000b000.etherne: scan phy mdio at address 9
=========> of_mdio.c of_mdiobus_register_phy() ENTER!
mdio_bus e000b000.etherne: scan phy mdio at address 10
=========> of_mdio.c of_mdiobus_register_phy() ENTER!
mdio_bus e000b000.etherne: scan phy mdio at address 11
=========> of_mdio.c of_mdiobus_register_phy() ENTER!
mdio_bus e000b000.etherne: scan phy mdio at address 12
=========> of_mdio.c of_mdiobus_register_phy() ENTER!
mdio_bus e000b000.etherne: scan phy mdio at address 13
=========> of_mdio.c of_mdiobus_register_phy() ENTER!
mdio_bus e000b000.etherne: scan phy mdio at address 14
=========> of_mdio.c of_mdiobus_register_phy() ENTER!
mdio_bus e000b000.etherne: scan phy mdio at address 15
=========> of_mdio.c of_mdiobus_register_phy() ENTER!
mdio_bus e000b000.etherne: scan phy mdio at address 16
=========> of_mdio.c of_mdiobus_register_phy() ENTER!
=========> of_mdio.c of_mdiobus_register_phy() registered phy mdio at address 16
=========> of_mdio.c of_mdiobus_register_phy() EXIT!
mdio_bus e000b000.etherne: scan phy mdio at address 17
=========> of_mdio.c of_mdiobus_register_phy() ENTER!
=========> of_mdio.c of_mdiobus_register_phy() registered phy mdio at address 17
=========> of_mdio.c of_mdiobus_register_phy() EXIT!
mdio_bus e000b000.etherne: scan phy mdio at address 18
=========> of_mdio.c of_mdiobus_register_phy() ENTER!
=========> of_mdio.c of_mdiobus_register_phy() registered phy mdio at address 18
=========> of_mdio.c of_mdiobus_register_phy() EXIT!
mdio_bus e000b000.etherne: scan phy mdio at address 19
=========> of_mdio.c of_mdiobus_register_phy() ENTER!
=========> of_mdio.c of_mdiobus_register_phy() registered phy mdio at address 19
=========> of_mdio.c of_mdiobus_register_phy() EXIT!
mdio_bus e000b000.etherne: scan phy mdio at address 20
=========> of_mdio.c of_mdiobus_register_phy() ENTER!
=========> of_mdio.c of_mdiobus_register_phy() registered phy mdio at address 20
=========> of_mdio.c of_mdiobus_register_phy() EXIT!
mdio_bus e000b000.etherne: scan phy mdio at address 21
=========> of_mdio.c of_mdiobus_register_phy() ENTER!
=========> of_mdio.c of_mdiobus_register_phy() registered phy mdio at address 21
=========> of_mdio.c of_mdiobus_register_phy() EXIT!
mdio_bus e000b000.etherne: scan phy mdio at address 22
=========> of_mdio.c of_mdiobus_register_phy() ENTER!
=========> of_mdio.c of_mdiobus_register_phy() registered phy mdio at address 22
=========> of_mdio.c of_mdiobus_register_phy() EXIT!
mdio_bus e000b000.etherne: scan phy mdio at address 23
=========> of_mdio.c of_mdiobus_register_phy() ENTER!
mdio_bus e000b000.etherne: scan phy mdio at address 24
=========> of_mdio.c of_mdiobus_register_phy() ENTER!
mdio_bus e000b000.etherne: scan phy mdio at address 25
=========> of_mdio.c of_mdiobus_register_phy() ENTER!
mdio_bus e000b000.etherne: scan phy mdio at address 26
=========> of_mdio.c of_mdiobus_register_phy() ENTER!
mdio_bus e000b000.etherne: scan phy mdio at address 27
=========> of_mdio.c of_mdiobus_register_phy() ENTER!
=========> of_mdio.c of_mdiobus_register_phy() registered phy mdio at address 27
=========> of_mdio.c of_mdiobus_register_phy() EXIT!
mdio_bus e000b000.etherne: scan phy mdio at address 28
=========> of_mdio.c of_mdiobus_register_phy() ENTER!
mdio_bus e000b000.etherne: scan phy mdio at address 29
=========> of_mdio.c of_mdiobus_register_phy() ENTER!
=========> of_mdio.c of_mdiobus_register_phy() registered phy mdio at address 29
=========> of_mdio.c of_mdiobus_register_phy() EXIT!
mdio_bus e000b000.etherne: scan phy mdio at address 30
=========> of_mdio.c of_mdiobus_register_phy() ENTER!
mdio_bus e000b000.etherne: scan phy mdio at address 31
=========> of_mdio.c of_mdiobus_register_phy() ENTER!
=========> of_mdio.c of_mdiobus_register() EXIT!
macb e000b000.ethernet eth0: Cadence GEM rev 0x00020118 at 0xe000b000 irq 148 (00:0a:35:00:1e:53)
macb e000b000.ethernet eth0: attached PHY driver [Generic PHY] (mii_bus:phy_addr=e000b000.etherne:10, irq=-1)
e1000e: Intel(R) PRO/1000 Network Driver - 3.2.6-k
e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
ehci-pci: EHCI PCI platform driver
usbcore: registered new interface driver usb-storage
mousedev: PS/2 mouse device common for all mice
i2c /dev entries driver
cdns-i2c e0004000.i2c: 400 kHz mmio e0004000 irq 141
Xilinx Zynq CpuIdle Driver started
sdhci: Secure Digital Host Controller Interface driver
sdhci: Copyright(c) Pierre Ossman
sdhci-pltfm: SDHCI platform and OF driver helper
sdhci-arasan e0100000.sdhci: No vmmc regulator found
sdhci-arasan e0100000.sdhci: No vqmmc regulator found
mmc0: SDHCI controller on e0100000.sdhci [e0100000.sdhci] using ADMA
ledtrig-cpu: registered to indicate activity on CPUs
usbcore: registered new interface driver usbhid
usbhid: USB HID core driver
NET: Registered protocol family 17
=========> dsa.c dsa_init_module() ENTER!
=========> dsa.c dsa_probe() ENTER!
Distributed Switch Architecture driver version 0.1
=========> dsa.c dsa_of_probe() ENTER!
=========> dsa.c dsa_of_probe() mdio = of_parse_phandle(dsa,mii-bus)!
=========> mdio_bus.c of_mdio_find_bus() ENTER!
=========> mdio_bus.c if (!mdio_bus_np) = mii_bus pointer = OK!
=========> mdio_bus.c d = class_find_device = NULL EXIT!
=========> dsa.c dsa_probe() ret = dsa_of_probe(&pdev->dev) = -517!
can: controller area network core (rev 20120528 abi 9)
NET: Registered protocol family 29
can: raw protocol (rev 20120528)
can: broadcast manager protocol (rev 20120528 t)
can: netlink gateway (rev 20130117) max_hops=1
Registering SWP/SWPB emulation handler
=========> dsa.c dsa_probe() ENTER!
=========> dsa.c dsa_of_probe() ENTER!
=========> dsa.c dsa_of_probe() mdio = of_parse_phandle(dsa,mii-bus)!
=========> mdio_bus.c of_mdio_find_bus() ENTER!
=========> mdio_bus.c if (!mdio_bus_np) = mii_bus pointer = OK!
=========> mdio_bus.c d = class_find_device = NULL EXIT!
=========> dsa.c dsa_probe() ret = dsa_of_probe(&pdev->dev) = -517!
hctosys: unable to open rtc device (rtc0)
ALSA device list:
  No soundcards found.
Freeing unused kernel memory: 2692K (c0689000 - c092a000)
INIT: version 2.88 booting
bootlogd: cannot allocate pseudo tty: No such file or directory
Creating /dev/flash/* device nodes
random: dd urandom read with 0 bits of entropy available
hwclock: can't open '/dev/misc/rtc': No such file or directory
Starting internet superserver: inetd.
INIT: Entering runlevel: 5
Configuring network interfaces... udhcpc (v1.23.2) started
Sending discover...
Sending discover...
Sending discover...
No lease, forking to background
done.
hwclock: can't open '/dev/misc/rtc': No such file or directory

petalinux_out_serial_eth_2016_1 login: 

 

Note that;

 

When I checked the devices found on mdio_bus, devices registers some of them PHY, some is global control registers seen as below

oot@petalinux_out_serial_eth_2016_1:~# ls /sys/bus/mdio_bus/devices/
e000b000.etherne:10  e000b000.etherne:13  e000b000.etherne:16
e000b000.etherne:11  e000b000.etherne:14  e000b000.etherne:1b
e000b000.etherne:12  e000b000.etherne:15  e000b000.etherne:1d

 

current ifconfig

root@petalinux_out_serial_eth_2016_1:~# ifconfig
eth0      Link encap:Ethernet  HWaddr 00:0A:35:00:1E:53  
          UP BROADCAST MULTICAST  MTU:1500  Metric:1
          RX packets:0 errors:0 dropped:0 overruns:0 frame:0
          TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
          collisions:0 txqueuelen:1000
          RX bytes:0 (0.0 B)  TX bytes:0 (0.0 B)
          Interrupt:148 Base address:0xb000

lo        Link encap:Local Loopback  
          inet addr:127.0.0.1  Mask:255.0.0.0
          UP LOOPBACK RUNNING  MTU:65536  Metric:1
          RX packets:0 errors:0 dropped:0 overruns:0 frame:0
          TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
          collisions:0 txqueuelen:0
          RX bytes:0 (0.0 B)  TX bytes:0 (0.0 B)

 

Is there anyone can suggest about this thread???

thanks,

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Participant idogan
Participant
7,410 Views
Registered: ‎03-09-2016

Re: zynq and marvell dsa 88e6352 integration, device tree

Jump to solution

Hi,

 

zynq and marvell 88e6352 ethernet switch integration is completed partially. Partially means that our custom board has two marvell ethernet switches (88e6352), one is connected to MIO and other is EMIO used with gmii2rgmii ip core and hey have seperate MDIO bus.

 

Currently, we have completed the integration for MIO connected one, that is we are successfully running ethernet switch which is connected to MIO. Works for the EMIO are in still progress. Below you can find the steps for the MIO connected switch integration;

 

********************************************

This info is related to solution about using Using GEM routed via MIO to the marvell ethernet switch 88e6352. Before solution steps, let me give our board setup between zynq7045 and marvell eth. switch 88e6352.

 

Our board setup:
Zynq PS GEM0 is connected to port5 of the marvell 88e6352 switch. Port5 of the switch is PHYless, it is a MAC, thefore our PS GEM0 and Port5-Switch connection is MAC-to-MAC (phyless) and digital interface between them is RGMII. Port0-toPort4 are normal PHY interface for outside phy interface. Since our board only use Port0-to-Port3, device tree does not include port4(lan4) node.

 

Zynq PS GEM1 is also connected to port5 of the second marvell 88e6352 switch. Since GEM1 is routed via EMIO on the board, gmii2rgmii IP core is used to establish RGMII connection between the GEM1 and the switch.

 

|————————————————————|              |——————————————————————————————————————————|
|     e000b000, GEM0—|———— RGMII ———|—port5 (0x15,act as MAC)        port0 —— PHY0
| Zynq-7045          |              |                  mv88e6352     ...       |
|     e000c000, GEM1 |———|          | port6 (disabled)               port3 —— PHY3 (port4 is not used)
|————————————————————|   |          |—————————————————————————————————————————|

                                                  |

                                                  |

                                                  |           |——————————————————————————————————————————|
                         — RGMII ———|—port5 (0x15,act as MAC)        port0 —— PHY0
                                    |                  mv88e6352     ...       |
                                    | port6 (disabled)               port3 —— PHY3(port4 is not used)
                                    |—————————————————————————————————————————|

 

Solution Steps:

 

1)  Vivado 2017.1 and Petalinux 2017.1 is installed.

 

2)  DSA/switch related kernel configurations, given below, are enabled from the petalinux-config -c kernel;

 

      * Switch (and switch-ish) device support @ Networking support->Networking options
      * Distributed Switch Architecture @ Networking support->Networking options
      * Distributed Switch Architecture HWMON Support @ Networking support->Networking options->Distributed Switch Architecture  (actually this is optional feature to get such as temp monitoring from the switch device)
      * Marvell 88E6xxx Ethernet switch fabric support @ Device Drivers->Network device support->Distributed Switch Architecture drivers
      * Switch Global 2 Registers support @ Device Drivers->Network device support->Distributed Switch Architecture drivers->Marvell 88E6xxx Ethernet switch fabric support
      * Marvell devices @ Device Drivers->Network device support-> Ethernet driver support
      * Marvell MDIO interface support @ Device Drivers->Network device support-> Ethernet driver support->Marvell devices
      * MDIO Bus/PHY emulation with fixed speed/link PHYs @ Device Drivers->Network device support->PHY Device support and infrastructure

3)  MACB driver patch is applied according to the this link https://www.origin.xilinx.com/support/answers/69132.html


4)  Device tree modification is made on system-user.dtsi (withinproject-spec/meta-user/recipes-bsp/device-tree/files), given below and attached also;

/include/ "system-conf.dtsi"
/ {

    aliases {

        serial0 = &uart1; /* Add this if you want console from uart1 */

    };

        mdio1: mdio {

            compatible = "cdns,macb-mdio";

            reg = <0xe000b000 0x1000>;

            clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;

            clock-names = "pclk", "hclk", "tx_clk";

                #address-cells = <1>;

                #size-cells = <0>;

        };

};


&mdio1 {

    #address-cells = <1>;

    #size-cells = <0>;


    switch0: switch0@0 {

        compatible = "marvell,mv88e6085";

        #address-cells = <1>;

        #size-cells = <0>;

        reg = <0>;


        ports {

            #address-cells = <1>;

            #size-cells = <0>;

            port@0 {

                reg = <0>;

                label = "lan0";

            };


            port@1 {

                reg = <1>;

                label = "lan1";

            };


            port@2 {

                reg = <2>;

                label = "lan2";

            };


            port@3 {

                reg = <3>;

                label = "lan3";

            };


            switch0phy5: port@5 {

                reg = <5>;

                label = "cpu";

                ethernet = <&gem0>;

                fixed-link {

                    speed = <1000>;

                    full-duplex;

                 };

            };

        };

    };

};


&gem0 {

        phy-mode = "rgmii-id";

       phy-handle = <&switch0phy5>;

};


5) The critical point: Because the connection between zynq and port5 of the switch is rgmii-id, there should be delay between data and clock signals. In order to that, related register should be set on switch 88e6352 so that switch 88e6352 can apply internally this delay. For now, it is made manually on u-boot stage by stopping booting on u-boot and writing "mii write 0x15 0x01 0xC003". 0xC003 updates the related register by setting delay bits.

 

Of course, this should be made automatically, may be using "marvell,reg-init = <...>" within device tree. However, it is not tried yet.

6) Then, finally boot to kernel from the u-boot by writing "run bootcmd", kernel boot is started and correct switch is found and printed on console in spite of compatible = "marvell,mv88e6085" given in device tree but it is ignored actually and talk with switch and found correct switch.


7) After login, ifconfig -a lists all eth0 and lan0-to-lan3 interfaces. After that, It is enough to set ip addresses for lan interfaces; e.g. "ifconfig lan0 192.168.2.21",  "ifconfig lan1 192.168.1.33", etc... ping is made successfully between zynq and those lan interfaces through eth0 rgmii interface.
********************************************


Device tree and console output files are attached.

GEM1 related info will be also put on this post, when it is ended up.

 

thanks,

 

 

 

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Participant idogan
Participant
11,156 Views
Registered: ‎03-09-2016

Re: zynq and marvell dsa 88e6352 integration, device tree

Jump to solution

Hi,

 

zynq and marvell 88e6352 ethernet switch integration is completed fully with some problems and their solutiıons and workarounds. . Below you can find the steps for GEM0 and GEM1 integration with their switches;

 

********************************************

Our board setup:

|————————————————————|              |——————————————————————————————————————————|
|     e000b000, GEM0—|———— RGMII ———|—port5 (0x15,act as MAC)        port0 —— PHY0
| Zynq-7045          |              |    mv88e6352 (switch1@addr=2)  ...       |
|     e000c000, GEM1 |———|          | port6 (disabled)               port3 —— PHY3(port4 is not used)
|————————————————————|   |          |—————————————————————————————————————————|

                                                  |

                                                  |

                                                  |          |——————————————————————————————————————————|
                         — RGMII ———|—port5 (0x15,act as MAC)        port0 —— PHY0
                                    |    mv88e6352 (switch2@addr=4)  ...       |
                                    | port6 (disabled)               port3 —— PHY3(port4 is not used)
                                    |—————————————————————————————————————————|

 

 

      * GEM0 is connected to the switch1 with RGMII-MIO signals. GEM0 controls the switch1 over GEM0 MDIO bus via MIO pins. Switch1 addres is 2.
      * GEM1 is connected to the switch2 with RGMII-EMIO signals. In order to do that, GMII2RGMII ip core v4.0 inside the PL side of the zynq is used between GEM1 and the switch2(not shown above graph but there is). GEM1 controls the switch2 over GEM1 MDIO bus via EMIO pins. 
Switch1 addres is 4.

      * That is, GEM0 and GEM1 has separate MDIO buses, this is not shared MDIO design.

      * Our aim is to establish fixed 1000mbps link between port5 of the switches and GEMs of the zynq.

      * Port5 of the switch is not a PHY, it is a MAC. That is, this is a MAC-to-MAC(PHYless) link between GEMs and port5 of the switches over RGMII interface.

      * Port4 of the switches are not used, so they are disabled.

      * Port0-to-Port3 of the switches have internal PHYs. Those are the ethernet interfaces to the outside.

 

Solution Steps:

 

1)  Vivado 2017.2 and Petalinux 2017.2 is installed.

 

2)  DSA/switch and GMII2RGMII related kernel configurations, given below, are enabled from the petalinux-config -c kernel;

 

      * Switch (and switch-ish) device support @ Networking support->Networking options
      * Distributed Switch Architecture @ Networking support->Networking options
      * Distributed Switch Architecture HWMON Support @ Networking support->Networking options->Distributed Switch Architecture  (actually this is optional feature to get such as temp monitoring from the switch device)
      * Marvell 88E6xxx Ethernet switch fabric support @ Device Drivers->Network device support->Distributed Switch Architecture drivers
      * Switch Global 2 Registers support @ Device Drivers->Network device support->Distributed Switch Architecture drivers->Marvell 88E6xxx Ethernet switch fabric support
      * Marvell devices @ Device Drivers->Network device support-> Ethernet driver support
      * Marvell MDIO interface support @ Device Drivers->Network device support-> Ethernet driver support->Marvell devices
      * MDIO Bus/PHY emulation with fixed speed/link PHYs @ Device Drivers->Network device support->PHY Device support and infrastructure

      * Xilinx GMII2RGMII converter driver @ Device Drivers->Network device support->PHY Device support and infrastructure

 

Last one is required for the xilinx gmii2rgmii ip core.

 

3)  MACB driver patch is applied according to the this link https://www.origin.xilinx.com/support/answers/69132.html

 

4)  Device tree modification is made on system-user.dtsi (withinproject-spec/meta-user/recipes-bsp/device-tree/files), given below and attached also;

 

/include/ "system-conf.dtsi"
/ {
        newmdio0: mdio0 {
            compatible = "cdns,macb-mdio";
            reg = <0xe000b000 0x1000>;
            clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
            clock-names = "pclk", "hclk", "tx_clk";
                #address-cells = <1>;
                #size-cells = <0>;
        };

        newmdio1: mdio1 {
            compatible = "cdns,macb-mdio";
            reg = <0xe000c000 0x1000>;
            clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
            clock-names = "pclk", "hclk", "tx_clk";
                #address-cells = <1>;
                #size-cells = <0>;
        };
};

/delete-node/ &ps7_ethernet_1_mdio;

&newmdio0 {
    #address-cells = <1>;
    #size-cells = <0>;

    switch0: switch0@2 {
        compatible = "marvell,mv88e6085";
        #address-cells = <1>;
        #size-cells = <0>;
        reg = <2>;

        dsa,member = <0 0>;

        ports {
            #address-cells = <1>;
            #size-cells = <0>;
            port@0 {
                reg = <0>;
                label = "lan0";
            };

            port@1 {
                reg = <1>;
                label = "lan1";
            };

            port@2 {
                reg = <2>;
                label = "lan2";
            };

            port@3 {
                reg = <3>;
                label = "lan3";
            };

            switch0phy5: port@5 {
                reg = <5>;
                label = "cpu";
                ethernet = <&gem0>;
                phy-mode = "rgmii-id";
                fixed-link {
                    speed = <1000>;
                    full-duplex;
                 };
            };
        };
    };
};

&gem0 {
    local-mac-address = [00 0a 35 00 1e 53];
    phy-handle = <&switch0phy5>;
};

&newmdio1 {
    #address-cells = <1>;
    #size-cells = <0>;

    switch1: switch1@4 {
        compatible = "marvell,mv88e6085";
        #address-cells = <1>;
        #size-cells = <0>;
        reg = <4>;

        dsa,member = <1 0>;

        ports {
            #address-cells = <1>;
            #size-cells = <0>;
            port@0 {
                reg = <0>;
                label = "lan4";
            };

            port@1 {
                reg = <1>;
                label = "lan5";
            };

            port@2 {
                reg = <2>;
                label = "lan6";
            };

            port@3 {
                reg = <3>;
                label = "lan7";
            };

            switch1phy5: port@5 {
                reg = <5>;
                label = "cpu";
                ethernet = <&gem1>;
                phy-mode = "rgmii-id";
                fixed-link {
                    speed = <1000>;
                    full-duplex;
                 };
            };
        };
    };

    gmiitorgmii0: gmiitorgmii@8 {
        compatible = "xlnx,gmii-to-rgmii-1.0";
        reg = <8>;
    };
};

&gem1 {
    local-mac-address = [00 0a 35 00 1e 55];
    gmii2rgmii-phy-handle = <&gmiitorgmii0>;
    phy-handle = <&switch1phy5>;        
};

&qspi {
    u-boot,dm-pre-reloc;
    #address-cells = <1>;
    #size-cells = <0>;
    flash0: flash@0 {
        compatible = "spansion,s25fl512s";
        reg = <0x0>;
        #address-cells = <1>;
        #size-cells = <1>;
        spi-max-frequency = <50000000>;
        partition@0x00000000 {
            label = "boot";
            reg = <0x00000000 0x00d00000>;
        };
        partition@0x00d00000 {
            label = "bootenv";
            reg = <0x00d00000 0x00040000>;
        };
        partition@0x00d40000 {
            label = "kernel";
            reg = <0x00d40000 0x00a80000>;
        };
        partition@0x017c0000 {
            label = "spare";
            reg = <0x017c0000 0x00000000>;
        };
    };
};

 

5) The critical point: Because the connection between zynq and port5 of the switch is rgmii-id, there should be delay between data and clock signals. In order to that, related register bits should be set on switch 88e6352 so that switch 88e6352 can apply internally this delay.

Before this was done manually using mii command at u-boot stage(mii write 0x15 0x01 0xC003), because the kernel could not set fixed-link port5 register for enable TX and RX clk delay. The reason of this analyzed and found the problem as;

 

       * There is a function for the fixed-link port settings of the switches called "mv88e6xxx_adjust_link()" within the "chip.c" (...build/tmp/work-shared/plnx_arm/kernel-source/drivers/net/dsa/mv88e6xxx/chip.c).
       * Within this "mv88e6xxx_adjust_link()" function, in order to be set fixed-link port register for TX/RX clk delays, "phydev->interface" value should come to here correctly.
       * By putting printk, I realized that phydev->interface value is "NA" (val = 0), therefore the TX/RX clk delay bits are not set.
       * "phydev->interface" value is set within dsa_cpu_dsa_setup() function within "dsa.c" by calling "of_get_phy_mode()" func. from the "of_net.c".
       * "of_get_phy_mode()" func. from the "of_net.c" looks for "phy-mode" string of the device node.
       * Since previously there was not given "phy-mode" property within the port5 node of the switch, "phy-mode" was became "NA".

 

Solution:

       * By putting phy-mode = "rgmii-id" into the port5 of the switch1 and switch2 in the device tree, TX and RX clk delay bits are set correctly.
       * After that, GEM0 ping successfully with PC but GEM1 still could not.
       * GEM1 problem and its workaround is related about gmii2rgmii driver explained in below.

 

6) GEM1 problem related about kernel panic which result from the xilinx gmii2rgmii driver, and also gmii2rgmii speed could not be set 1000mbps, it was always 10mbps. Since switch port5 fixed link speed is 1000mbps, but gmii2rgmii speed is 10mbps, GEM1 could not ping with PC.

 

       * When the "phy-handle" property was put into the gmii2rgmii node in device tree, kernel panic was occured at the "memcpy" within "xgmiitorgmii_probe()" function in the xilinx_gmii2rgmii.c
       * In order to prevent it, "phy-handle" property is moved into the gem1 node in the device tree.
       * This time, xgmiitorgmii_probe() return with "Couldn't parse phy-handle" error. (dev_err(dev, "Couldn't parse phy-handle\n")). As a result of that, XILINX_GMII2RGMII_REG could not set with the speed value of MCR_SPEED1000.
       * Before the workaround, I had to use mii command at u-boot stage in order to set 1000mbps into the XILINX_GMII2RGMII_REG. (mii write 0x8 0x10 0x0040)

 

Workaround:

       * By putting  "phy-handle" property into the gem1 node in the device tree,  kernel panic is prevented, but xgmiitorgmii_probe() return with error "Couldn't parse phy-handle".
       * By adding "mdiobus_write()" function into the xgmiitorgmii_probe, before "Couldn't parse phy-handle" error return, XILINX_GMII2RGMII_REG is forced to 1000mbps.
       * In order to do it, a patch file is generated. You can find it attached.
       * Of course, this is not a solution but a workaround.
       * After that, GEM1 also ping successfully with PC.

 

7) After login, ifconfig -a lists all eth0, eth1 and lan0-to-lan7 interfaces. After that, it is required to up eth1, e.g. "ifconfig eth1 up" Then, It is enough to set ip addresses for lan interfaces; e.g. "ifconfig lan0 192.168.0.20",  "ifconfig lan4 192.168.4.24", etc... ping is made successfully between zynq and those lan interfaces.

********************************************

 

Now, GEM0 and GEM1 ping is OK with PC by doing above steps. You can find the patch for the xilinx_gmii2rgmii.c, device tree and console output.

 

thanks,