zynqmp_phy: PLL lock time out + ZynqMPSoC 7EV custom platform
I created the DP port interface enabled vivado design and BSP for my custom 7EV platform. The below message from the log while booting which tells DP port is not configured properly.
xilinx-psgtr fd400000.zynqmp_phy: PLL lock time out [15.100543] xilinx-psgtr fd400000.zynqmp_phy: Lane:1 type:8 protocol:4 pll_locked:no [15.108284] zynqmp-display fd4a0000.zynqmp_phy: PLL lock time out [15.114824] zynqmp-display: probe of fd4a0000.zynqmp-display failed with error -110
I also make sure that I have done the kernel DP driver configuration as per the below link.