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Observer luckzzylb
Observer
131 Views
Registered: ‎08-14-2017

A question about PS DDR configuration of Zynq UltraScale plus MPSOC(ZU9EG)

Hi there,

we are using MIcron’s DDR4 (MT40A1G8WE-083E) in our MPSOC (ZU9EG) design. Now we have a question on how to set the slew rate of the IO for address/command pins. According to ug1087, the value of ACSR in ACIOCR0 (DDR_PHY) register controls can be set to select the slew rate.

ACIOCR0 Configuration Register.png

Because the ACSR has two bit width, the value can be set to 0x0, 0x1, 0x2 and 0x3. However, the meaning of each value is not given in the description of ACIOCR0 in ug1087. If we want to select the slew rate of address/command IO pins to the “Middle-slew”, which value should we use?

 

1 Reply
Moderator
Moderator
54 Views
Registered: ‎11-28-2016

Re: A question about PS DDR configuration of Zynq UltraScale plus MPSOC(ZU9EG)

Hello @luckzzylb ,

That register doesn't actually control the slew rate settings in this particular way and the actual implementation in the controller's PHY is much more sophisticated.  Fundamentally the PS DDR I/O settings are automatically generated to match your memory topology and no user intervention is required.  These are the tested, characterized, and supported I/O settings for the PS DDR controller that work in conjunction with a board that was laid out following the guidelines in UG583.  The IBIS file that's generated when using the write_ibis command with a synthesized/implemented PS DDR interface will automatically have the correct model selected.  Using any other settings is not supported by Xilinx and hasn't been tested or characterized.

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