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Visitor kmadhuri
Visitor
192 Views
Registered: ‎09-18-2018

AXI EMC v3.0 ip core

Hi ,

 We are using AXI EMC V3.0 controller  to interface  MICROBLAZE soft processor with micron flash( MT28FW02GBBA1HPC-0AAT) in  KINTEX FPGA. In AXI EMC V3.0 controller logic ip core document it is mentioned that , A0 pin should left unconnected when interfacing with 16 bit Flash chips.As per that   A1 pin of controller is connected to flash A0 pin,not able to read device ID itself.Then in SDK application if we shift the address  by one bit ,we could read the device ID.I am attaching Flash chip datasheet  for reference.

Earlier  we could interface  other Flash chip  by A0 pin  left unconnected as that chip don’t have A0 pin. Please advice how interface 16 bit chip which has A0 pin .

   Thanks

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2 Replies
Xilinx Employee
Xilinx Employee
127 Views
Registered: ‎10-30-2017

Re: AXI EMC v3.0 ip core

Hi @kmadhuri,

 

How do you mapped your signals? is MSB and LSB bits are mapped correctly.

Best Regards,
Srikanth
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Visitor kmadhuri
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99 Views
Registered: ‎09-18-2018

Re: AXI EMC v3.0 ip core

Hi Srikanth,

  

We have  mapped directly signals i.e.  MSB to MSB , LSB to LSB.EMC controller  A1 pin is mapped to Flash A0 and EMC controller  A26 pin is mapped to Flash A25  .Flash A26 is assigned  with zero, for selecting lower die .

I am attaching the Flash configuration file and XDC files for reference.

 

Thank you.

Madhuri

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