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Adventurer
Adventurer
5,383 Views
Registered: ‎04-20-2009

Accessing EMIO GPIO in Zynq

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Hi all!

Our SW guys have trouble controlling the EMIO GPIO in our system. They seem to be able to control the tri-state but have not been able to drive values to the connected pins.

 

- I have enabled 5 bits of EMIO GPIO in the I/O Peripherals pop-up of the Zynq tab inXPS and have connected the _I, _O and _T signals as three 5-bit vectors to external ports.

- On our top level I have instantiated 5 IOBUF where I have simply connected the I, O and T to the appropriate signals from the processing system and the IO to the external pins.

- I have set the pin location, IO-standard, drive strength etc. in the .ucf file and also enabled pull-up since that was wanted.

- Setting the DIRM and OE register bits high causes the GPIO pins to go low.

- Resetting the same register bits causes the GPIO pins to float, and the pull-up pulls them high. So far so good.

- Setting DATA, DIRM and OE register bits high should in my world set the GPIO pins high, but still causes the GPIO pins to go low.

- Setting the MASK_DATA as indicated (e.g.. FFE0001F to set all five of GPIO(4:0) low, might as well have set FFFF0000) and DIRM and OE register bits high should also in my word set the GPIO pins high, but still causes the GPIO pins to go low.

 

What am I missing here? We run ISE 14.3 and the device is a xc7z020-1clg400. And yes, I did try Google before posting!

 

Thanks!

/Lars

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Adventurer
Adventurer
6,988 Views
Registered: ‎04-20-2009

Re: Accessing EMIO GPIO in Zynq

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...and there it is, staring me in the face. The _O from processing_system_7 shall be connected to the _I of the IOBUF and v.v.

 

Silly me!

/Lars

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3 Replies
Adventurer
Adventurer
5,377 Views
Registered: ‎04-20-2009

Re: Accessing EMIO GPIO in Zynq

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New development!

In an attempt to prove my innocence I started on a ChipScope version to probe the I, O and T of the GPIO. Guess what? XST has done away with all but the T! Wonder how that happened?

 

Looking in the .syr file I notice two warnings, on about the GPIO O signal being unconected and one about the GPIO I signal being sourceless. I must have got my wires crossed, but I honestly can't see where. I am tempted to call it a synthesis bug, but from experience it is probably some silly error I have made myself.

 

Sorry!

/Lars

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Adventurer
Adventurer
6,989 Views
Registered: ‎04-20-2009

Re: Accessing EMIO GPIO in Zynq

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...and there it is, staring me in the face. The _O from processing_system_7 shall be connected to the _I of the IOBUF and v.v.

 

Silly me!

/Lars

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Observer tbernath
Observer
5,302 Views
Registered: ‎04-14-2008

Re: Accessing EMIO GPIO in Zynq

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Lars,

I'm struggling with something very similar.  Can you share a screen shot of the XPS Ports tab for the ethernet parts?

It would be greatly appreciated.

 

I am trying to connect the EMIO through the GMIItoRGMII IP to the PHY on the Zedboard.

 

Thanks,

Tracey

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