05-09-2014 03:18 PM
I have a question about customizing the Block Memory Generator core that is used to instantiate BRAM cores in designs. I intend to design a BRAM core that can hold 128*128 integers - which is 65536 (2^16) bytes.
How do I interpret the relationship between the width and depth numbers? I first interpreted them to be a BRAM where each address stores <width> bits, and it has <depth> addresses. This doesn't seem to be the case. To store a 128*128 block, I had to configure the BMC with a read/write width of 32 bits, depth of 65536.
From above, this means that the depth is measured in bytes, and is unrelated to the width. Now, I want to be able to configure the same BMC (128*128) to read out 256 bits from one read. If I just increase the read/write width to 256, the number of required block RAM resources shoots through the roof. At the same time, if I instantiate the BMC with a width of 256 and depth of 8192, I end up with a smaller BMC than required.
Can anyone explain how these parameters translate to the actual block RAMs used?
Is the depth supposed to be specified in total number of bytes?
How does the width affect the size of the block RAM? How does it affect the number of BRAM resources required?
05-09-2014 06:15 PM
A RAM is generally measured as depth x width. The width is the number of bits in the word, and the depth is the number of words in the RAM. So in your case, you want to store 128x128 words, with each word being 32 bits. This would be a 16,384x32 RAM.
If you want 256 bits at the same time (which corresponds to 8 integers), then you need a width of 256. But, since each RAM word is now 256 bits wide, you would want a RAM that has 1/8 the number of words - so 2048 words. Thus the RAM would be 2048x256.
Since each BRAM can store 32Kbits (36Kbits if you use parity), then both configurations would require 16 BRAMs. In the first case, the RAM generator would (probably) use 16 RAMs, with each RAM being 16,384x2 (putting the RAMs side by side). For the second configuration, it would probably use 16 RAMs with each RAM being 2048x16.
05-09-2014 07:08 PM
Thanks for the reply. Sticking to the 16384 x 32 BRAM - I would like to use CDMA to move data between BRAM and DDR on the Zynq (ZC706). Do I need to do anything special to configure the CDMA based on the word length? The DDR is byte-addressable, so each address corresponds to a byte. If the BRAM's word length is 32 (or 256), does that mean that each BRAM address corresponds to 4 bytes?
I am using CDMA SG transfer to copy a block of integers into the BRAM. I'm using the same pointer-based arithmetic to calculate the addresses of both DRAM and BRAM locations - meaning, I'm incrementing the address by 4 in both DRAM and BRAM to store consecutive integers. Is this wrong? Should I increment DRAM address by 4, and BRAM address by 1?
05-10-2014 07:59 AM
You are pretty focussed on "bytes"...
The addressing of a resource depends partly on the resource itself, and partly on what the controller does with it.
In the case of a block RAM, the addressing is as I described above; the width determines the size of the word, and the depth determines how many words are in the RAM. The addressing is word based, so if your RAM is 256 bits wide (i.e. the word size is 256), then address 0 gives you the first 256 bits, address 1 gives you the next 256 bits, address 2 the next 256... There is no (real) concept of bytes, except that the RAM does give you byte enables to be able to control the writing of the individual groups of 8 (or 9) bits in within an address.
The organization of SDRAM varies from system to system, based on performance and storage needs. You could have SDRAMs that are x16 wide, or wider (potentially even much wider). Things are even more complicated by the fact that modern SDRAMs are double data rate (DDR), so they do two read or write cycles per clock. From a system perspective this makes the RAM look like it is twice the width (a single x16 DDR-SDRAM can write 32 bits/clock cycle).
Since SDRAMs can be organized in many ways, and SDRAMs are often used for processor applications, the controllers for SDRAMs often present an interface that is byte accessible; the addresses presented to them are byte addresses, and the controller manipulates that into actual word addresses for the SDRAMs with the appropriate byte enables (or data masks). This is generally independent of the data bus widths of the controller (which may be different from that of the actual SDRAMs even when you take into account DDR).
So, while it really depends on the controllers and how things are used in the system, RAMs are usually addressed by their configured word width, and SDRAM controllers by bytes.
05-13-2014 11:33 AM
Thanks Avrum! That clarifies a lot of things for me. I'll need to look into the way addresses are being generated from my Vivado HLS design that interfaces with the wide BRAM.
05-16-2014 04:26 PM
12-10-2018 02:50 AM
hi! i'm doing image processing it's my first time so i creat RAM but i don't know how to put the parameters of block memory generator specially memory size from where i can found. please if you have idea help me thank you