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Visitor ryanchen1989
Registered: ‎07-31-2015

Communication between FPGA and processor



I am now trying to figure out how to realize data communication between FPGA and processor. I have a couple of questions:


1) I know we can use FPGA write OCM on PS through AXI interface. We can easily enable an AXI HP port of PS in block design. But, how can we configure OCM rather than DDR as the destination?

    Also what AXI IP core needs to be used in PL? I find some uses AXI register slice, some uses AXI data FIFO. 


2)  What functions need to be used in the software so that the processor can read data from OCM?


3) Is there any reference design that helps me to complete my design? I have searched online and found that most of the reference design only introduced how to use AXI GPIO or how to use FPGA to write DRAM.

    I have the Zedboard, but I do not have license for SDSoC, so I cannot try the TRD design.


Please help me. Thanks.



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Teacher muzaffer
Registered: ‎03-31-2012

Re: Communication between FPGA and processor

1) OCM has a fixed address. You need to map that address to the process' address space (mmap if linux, just the address itself if bare-metal I think). OCM & DDR have separate addresses.
As to AXI IP you need an AXI master to write to OCM. I suggest that you use the ACP instead of HP for this purpose.
2) Again OCM is mapped to a specific address. Software running on the processors just needs to read/write to that address to access OCM, nothing else.

Depending on where the data is originating, you can use possibly use a datamover to write it to OCM through ACP.
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