UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor mpefareo
Visitor
3,521 Views
Registered: ‎02-28-2011

DDR and FIXED_IO on processing_system7_1 ip

Hello, I have got probably simple question I can't answer.

We are talking about Zynq processot(ZC-702 board for example) and Vivado for design software.

Say, for example, for very simple design, we only have got UART1 and SD card interfaces on Processing system enabled(just enaough to talk to linux).

The question is: DDR and FIXED_IO is present on Block diagram and they have got dedicated pins, but UART1 and SDcard interface also have got "dedicated pin"(configured through IP configure menu). Why only DDR and FIXED_IO on the IP block and not other periferal interfaces? Do I miss something in here, is there any reson for that?

it is a stupid question , but I can't answer it. What is the difference between two of this periferal pin "classes"(DDR, FIXED_IO <=> Other periph(UART, SD card, SPI ...))

 

Thank you in advance

0 Kudos
2 Replies
Teacher muzaffer
Teacher
3,505 Views
Registered: ‎03-31-2012

Re: DDR and FIXED_IO on processing_system7_1 ip

It's mainly a decision made by Vivade designers. Even though it's possible to run the Zynq without DDR, a vast majority of users will use it with DDR (and the FIXED_IO stuff) but the rest of the IOs, even though they are dedicated, they maybe left unused by a significant portion of designs.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
0 Kudos
Visitor mpefareo
Visitor
3,485 Views
Registered: ‎02-28-2011

Re: DDR and FIXED_IO on processing_system7_1 ip

Thank you for your answer.

The confusing bit for me was the fact that those signals (DDR and FIXED_IO) when outside.

Say for example you have got a top.vhd as as top module in the design, wich instantiate zynq_design_wrapper.vhd.

DDR and FIXED_IO will just go straight to top.vhd port.

Now I think may be the reason is that this allows us to control properties of those pin on FPGA(standard, strength and others).

Again this is just my gues.

Thank you again for your answer.

0 Kudos