03-13-2018 09:45 AM
03-16-2018 08:01 AM
Have you verified that the PL controller and components are working as expected using our DDR4 IP Example Design? With this design you can verify that calibration is completing and you can also utilize the Advanced Traffic Generator to see if you get any data errors. If you do not run into any data errors or calibration issues in the PL alone, then I would say there is something wrong in your application with respect to PS to PL configuration.
04-10-2018 06:50 AM
This is from Vivado 2017.1, but this is the configuration I used. I had issues with my DDR4 and used the fsbl memory test program to verify operation. In 2017.1, the settings for the DDR memory does not properly change like it does for a Zynq-7000 device. Double check the settings closely.