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DDR4 zynq issue

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Visitor
Posts: 6
Registered: ‎04-12-2017

DDR4 zynq issue

We have developed a custom board with XCZU15EG-2FFVB1156 and MT40A1G8WE-083E-AIT-B DDR4. We have random errors when we do "mem test" by xilinx. We have done SI analysis and it's ok. We have checked the voltage and them are in range (ripple and value) and no spikes are present. What can we do to resolve the issue?
Thanks
Posts: 247
Registered: ‎02-11-2014

Re: DDR4 zynq issue

Hello @giampybg,

 

Have you verified that the PL controller and components are working as expected using our DDR4 IP Example Design? With this design you can verify that calibration is completing and you can also utilize the Advanced Traffic Generator to see if you get any data errors. If you do not run into any data errors or calibration issues in the PL alone, then I would say there is something wrong in your application with respect to PS to PL configuration.

 

Thanks,

Cory

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Visitor
Posts: 6
Registered: ‎04-12-2017

Re: DDR4 zynq issue

Hello coryb,

we don't use PL to control DDR4, but the dedicated controller on PS unit.

 

Thanks

Xilinx Employee
Posts: 652
Registered: ‎07-30-2007

Re: DDR4 zynq issue

Any other details? Did you use 50Ohm traces instead 40Ohm? Any other guidelines which were not followed from the PCB guide?
Adventurer
Posts: 59
Registered: ‎05-07-2008

Re: DDR4 zynq issue

Hello,

This is from Vivado 2017.1, but this is the configuration I used. I had issues with my DDR4 and used the fsbl memory test program to verify operation. In 2017.1, the settings for the DDR memory does not properly change like it does for a Zynq-7000 device. Double check the settings closely.

 

ZU_DDR4_settings.jpeg

Visitor
Posts: 6
Registered: ‎04-12-2017

Re: DDR4 zynq issue

Thanks, for your support but we have found the issue. There were a spikes on voltage came out from PMIC of the board that generated the issues.

 

Thanks