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Observer davidh1901
Observer
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Registered: ‎07-27-2008

DRAM supported by MPSoC/RFSOC

Hi,

 We're designing a board that uses the RFSoC, and we need to know what memory configurations are supported to get 8Gbytes of DDR.

I found this

https://www.micron.com/-/media/client/global/documents/products/other-documents/xilinx_compatibility_guide.pdf?la=en

which states that 32Gb density per chip is supported using LPDDR3 but if I try and configure it in vivado 2018.3, I can only select up to 12Gbit per chip.

We could use the DDR4 parts (micron MT40A family) but that would require a 16 Gb density (4 parts, 16 bit bus each). The 16 Gb density does not appear to be supported according to the document linked above and for the parts we can get Vivado complains that the allocation of address bits between the row and bank address is illegal:

  • CRITICAL WARNING: [PSU-1]  Setting of Bank Group Address Count (Parameter PSU__DDRC__BG_ADDR_COUNT) to 2 is not valid when the value of DRAM IC Bus Width (Parameter PSU__DDRC__DRAM_WIDTH) is set to 16. The valid value for Bank Group Address Count (Parameter PSU__DDRC__BG_ADDR_COUNT) is 1.
  • CRITICAL WARNING: [PSU-2]  Setting of DDR Row Address Count (Parameter PSU__DDRC__ROW_ADDR_COUNT) to 16 is not valid when the value of Device Capacity (Parameter PSU__DDRC__DEVICE_CAPACITY) is set to 16384. The valid value for Row Address Count (Parameter PSU__DDRC__ROW_ADDR_COUNT) is 17.

 

Is there any other documentation available on supported parts ? Or are the values allowed in the PS configuration GUI for Vivado 2018.3 overly restrictive ?

 

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