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Visitor tervoa
Visitor
3,305 Views
Registered: ‎01-23-2017

Debugging custom AXI4 master on Z7020

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I have a custom AXI master IP running on a PYNQ-Z1 board. The AXI master is connected to the PS AXI3 slave port (S_GP0) and through that, attempts to access PL peripherals. It attempts to read 16 words (32b) of data from a BRAM block mapped (through an AXI BRAM controller) to 0x4000_0000, and write that data back to the same block, next to the read data (0x4000_0020 onwards). I've been trying to debug the behaviour with an ILA core and AXI protocol checkers, and am running out of ideas at the moment.

 

When connected directly to the BRAM controller, the read/write transfers succeed without an error. When connected through interconnects and the PS, the read transfer succeeds, but the write transfer doesn't. The interconnect connected to the custom IP has a 32 word deep FIFO, so the it accepts all write data. However, while the address and control packet is forwarded to the PS/AXI3 side of the interconnect (all data seems to be as it should, AWVALID is high), AWREADY stays low, i.e. the PS doesn't even accept the address and control packet.

 

I have AXI protocol checkers connected to both interfaces, and the only errors they give are on bits 58 and 59, i.e. AXI_ERRS_RDATA_NUM and AXI_ERRS_RID. I'm not entirely sure why this happens, as they activate mid-burst without any reason (there are 16 read strobes visible, and ARLEN is 0x0f when ARVALID is high). Anyway, both errors comment on the read channel and seemingly on signals produced by Xilinx IP, so it seems safe to ignore those.

 

Any advice is appreciated.

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Visitor tervoa
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5,873 Views
Registered: ‎01-23-2017

Re: Debugging custom AXI4 master on Z7020

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Figured out the problem: this was solved by replacing the bitstream in boot.bin, which - I guess - had different settings for PS than my design.

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Voyager
Voyager
3,259 Views
Registered: ‎04-21-2014

Re: Debugging custom AXI4 master on Z7020

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Why do you want to access a PL slave from a PL master through the PS?  I say this because it seems to me it would be more efficient to just keep it in PL.

 

But back to what you're asking:

The AXI interconnect should do protocol conversion.  But you might change the fifo depth to 256.  AXI3 max burst size is 16.  However this may be pointless if the first transactions don't get a ready.

 

Another idea is to connect a DMA in place of your custom AXI master, and using VLA, do a comparison between the DMA and your AXI master. 

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-23-2012

Re: Debugging custom AXI4 master on Z7020

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Can you please share the block diagram and scopeshots of ILA? This would give me some clarity on your system to provide suggestions.
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Visitor tervoa
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Registered: ‎01-23-2017

Re: Debugging custom AXI4 master on Z7020

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I'm accessing PL through PS partly for design simplicity (one AXI interface for all accesses) and because the current test platform doesn't have any memory reserved from the OS or a kernel-mode driver so modifying random physical addresses is a bit hazardous. Accesses to DRAM address space seem to result in the same outcome, and I will need access to that eventually.

 

Block diagram and ILA screenshots attached, one from each side of the custom IP - ARM interconnect and their respective protocol checkers.

block_design.png
ILA_ARM.png
ILA_custom_ip.png
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Visitor tervoa
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Registered: ‎01-23-2017

Re: Debugging custom AXI4 master on Z7020

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Figured out the problem: this was solved by replacing the bitstream in boot.bin, which - I guess - had different settings for PS than my design.

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Participant jpan127
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Registered: ‎05-28-2017

Re: Debugging custom AXI4 master on Z7020

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Hi, can you elaborate on your solution? I believe I have a similar issue.
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