12-20-2017 04:36 PM
I'm working on a project, in which we need to use the microblaze read the data from a VHDL block made by ourselves.
What I did is: I went to a file named xxxxx_S00_AXI.vhd and found a process that working on assigning different value to "reg_data_out", and replace the first variable by what I want to sent to microblaze.
Microblaze does get something from The VHDL block, but not what we expected : whenever microblaze wants to get data, the VHDL block will give it. For example, variable 'output_data' is what we wanna send to microblaze. And usually it is "00000000", we it is triggered by some other blocks, it will become "1100xxxx" (xxxx part depends on the input data), and this is what we want to send to the microblaze instead of '00000000'. What I think the axi will do is there should be a 'valid bit' for the VHDL to tell the microblaze when the data are ready, however I did not find it, and microblaze keeps reading "00000000" when it reaches the command for reading.
Though I made some 'while loops' as the 'handshaking protocols' to stop the microblaze from reading the meaningless data from the VHDL, we still get error from it.
The interface on VHDL block is a slave one, and the microblaze gets the master one.
Did I miss something in the documents? or is it the correct way to replace the variable in 'xxxxx_S00_AXI.vhd' to sent the data to microblaze? I'm really confused by it..
12-20-2017 05:08 PM - edited 12-20-2017 05:31 PM
@khc9355 When you say that the vhdl is a "slave", are you saying that your VHDL IP implements an AXI-full slave interface? Memory mapped or streaming?
Can you share a screenshot of your design?
12-20-2017 08:00 PM
12-20-2017 08:08 PM - edited 12-20-2017 09:53 PM
In addition to the videos below, on this one I teach how to modify an AXI lite default component and inject your logic.
12-21-2017 02:22 PM
It should be as simple as replacing the slv_reg0 with your 'custom_signal' in the reg_data_out read mux.
But, make sure that you have routed custom_signal out of xxxx_S00_AXI.vhd and through custom_core.vhd with the correct directions.
You could try to repackage the IP, and while in the packager vivado project, synthesis your IP, open synthesis, and press 'F4' to review the schematic and make sure the mux is receiving the signal that you expect.
12-21-2017 03:18 PM
12-21-2017 03:55 PM
The axi interface will only use the read data when rvalid AND rready is high. So depending on pipelining and such, you could get early knowledge that a read access is starting by looking for arvalid. Once you capture your custom signal in FFs before the read mux, then allow the core to create rvalid.
BUT: make sure that you only have rvalid AND rready high for one clock cycle. If rvalid AND rready are high for multiple clock cycles, then it will confuse the axi infrastructure because it will think there is already data available for the next address transaction.