05-19-2017 07:48 AM - edited 05-19-2017 08:25 AM
I develop a firmware for the UltraScale+ SoC with multiple Ethernets connected via SFP.
Unfortunately, the block diagram was quite complicated. Below is the version simplified to a single Ethernet:
To allow the end-user to easily copy the Ethernet block to his full design, I have moved the Ethernet interfaces with the surrounding infrastructure to the hierarchical sub-block. Below is again the simplified version:
It appeared, however, that the block copied to the final design does not work correctly. The PCS/PMA PHY was not recognized.
I have checked my hierarchical design, and it was working correctly, but when I removed the connection between the MDIO_ENET0 port in the PS and the mdio_pcs_pma port in the ether sub-block, the same problem happened.
I have investigated implemented designs, and have found that the MDIO interface is connected correctly in the first design:
But not in the last one:
Of course the same problem occured, when the end-user has connected the ports of the copied block in his full design.
It seems, that the Block Designer does not connect correctly the MDIO interfaces through the hierarchy boundaries.
Probably it is somehow associated with the definition of the "xilinx.com:interface:mdio_rtl:1.0" interface.
I attach the sources of the affected design.