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Observer moritz_fischer
Observer
9,965 Views
Registered: ‎02-20-2014

MIO and Ethernet 0 reset with Vivado 2015.2/3

I'm trying to bring up a new board using a Micrel KSZ9031 ethernet PHY connected via MIO to my Zynq.

I configured MIO6 to be ENET0 reset (LVCMOS 1.8V, slow, pullup disabled (cannot be changed), out, Active LOW).

 

Now independent of whether I select 'Active High, or Active Low' the generated ps7_init_gpl files look *exactly* the same?!

The generated .xci file changes depending on the setting.

I hooked up a scope and I cannot see the pin wiggle either, so I'm starting to wonder if there's something wrong.

 

Is my assumption that the FSBL should toggle the reset and leave it either high, or low depending on the 'Active high/low' setting wrong?

 

Thanks,

 

Moritz

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7 Replies
Teacher muzaffer
Teacher
9,936 Views
Registered: ‎03-31-2012

Re: MIO and Ethernet 0 reset with Vivado 2015.2/3

probably, it will cause a change in the dts file and let the (linux) driver to handle reset instead of fsbl.
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Observer moritz_fischer
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9,930 Views
Registered: ‎02-20-2014

Re: MIO and Ethernet 0 reset with Vivado 2015.2/3

I don't see either the macb or the xilinx_emacps driver using the gpio property. Am I missing something here?

Would it be up to the phy driver? Is there some devicetree magic I'm not getting?

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Teacher muzaffer
Teacher
9,924 Views
Registered: ‎03-31-2012

Re: MIO and Ethernet 0 reset with Vivado 2015.2/3

I don't think it would be in the mac driver. Phy driver is a lot more likely. They would probably assume the polarity of the reset so no magic is needed.
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Observer moritz_fischer
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9,915 Views
Registered: ‎02-20-2014

Re: MIO and Ethernet 0 reset with Vivado 2015.2/3

I did a git grep on both mainline and xilnix tree, the string 'enet-reset' or 'xlnx,enet-reset' doesn't show up. If *anything* picks it up from the dts I'd expect it to show up. Any other ideas?

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Scholar vanmierlo
Scholar
6,065 Views
Registered: ‎06-10-2008

Re: MIO and Ethernet 0 reset with Vivado 2015.2/3

I can only confirm that with petalinux 2016.2 this is still the same. The generated code does not change whether the reset is configured active-low or active-high. Not for the FSBL and not for the device-tree.

 

I do see some wiggling of the reset line which is correct for an active-low reset.

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Newbie ngxbac
Newbie
6,051 Views
Registered: ‎09-12-2016

Re: MIO and Ethernet 0 reset with Vivado 2015.2/3

I also got them same. 'enet-reset' or 'xlnx,enet-reset' seem not working. When I check status of GPIO reset.
- active_low = 0
- direction = in
- value = 0

It seems that it can not reset.
I tried to add the code at FSBL to reset GPIO, but it does not work.
Is there anybody has another ideas to do this?.
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Scholar vanmierlo
Scholar
5,858 Views
Registered: ‎06-10-2008

Re: MIO and Ethernet 0 reset with Vivado 2015.2/3

In my case the FSBL does generate the reset (without any manual interventions on the generated code). But it is always for an active-low reset. And u-boot or linux have no knowledge of the reset and thus do not generate it.

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