10-22-2017 05:03 AM
I have designed an AXI slave core in Vivado_HLS and I want to integrate it with the PCIe to AXI to be used as an PCIe accelerator card (KC705). All of the examples designs I have seen so far use DMA and DDR3 memory and a microprocessor (microblaze or zynq). What am interested in accomplishing is interfacing AXI memory mapped to PCI Express (pcie_axi) with my core to send/receive data without using a mP and DMA.
So far, I've tested successfully AP65444 driver with a PCI/DMA subsystem for PCI Express (xdma) based design but I couldn't find any official Xilinx driver for AXI memory mapped to PCI Express except this one https://github.com/strezh/XPDMA which again uses DMA.
Would it possible to use either one of these drivers without DMA and DDR3 and how should I configure the BARs to send/receive data to my core?
This is the Vivado design for your convenience.
10-22-2017 09:52 AM
@delk You can expand the AXI MM component and see what's inside.
There are two other pci express components in Vivado that will give you direct access to PCI-e streaming interface but you will have to go through the entire pci-express protocol to decode it.
See the docs here.
10-22-2017 10:37 AM
Is there any ready driver I could you for to stream data from the PCIe to my core using AXI MM? Alternatively, is there any workaround in order to use the AR56444 driver with the xdma connected to my core (instead of the DDR3 memory) to send/receive data?
10-22-2017 10:52 AM
10-22-2017 11:13 AM
10-22-2017 11:35 AM
OK, so BAR0 will translate to my core or BRAM It is not very clear to me how the address space should be. When I use for example dma_to_device to send data, is the mapped address of my core or BRAM the right address I should be sending data to?
10-23-2017 05:50 PM
@delk That I am not sure brother. It has been a while I dealt with this PCI-e driver. But there are examples in the code, have a look.