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Observer delk
Observer
1,637 Views
Registered: ‎02-05-2014

PCIe accelerator

I have designed an AXI slave core in Vivado_HLS and I want to integrate it with the PCIe to AXI to be used as an PCIe accelerator card (KC705). All of the examples designs I have seen so far use DMA and DDR3 memory and a microprocessor (microblaze or zynq). What am interested in accomplishing is interfacing AXI memory mapped to PCI Express (pcie_axi) with my core to send/receive data without using a mP and DMA. 

 

So far, I've tested successfully AP65444 driver with a PCI/DMA subsystem for PCI Express (xdma) based design but I couldn't find any official Xilinx driver for AXI memory mapped to PCI Express except this one https://github.com/strezh/XPDMA which again uses DMA.

 

Would it possible to use either one of these drivers without DMA and DDR3 and how should I configure the BARs to send/receive data to my core?

 

This is the Vivado design for your convenience.

 

 

 

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7 Replies
Scholar hbucher
Scholar
1,617 Views
Registered: ‎03-22-2016

Re: PCIe accelerator

@delk You can expand the AXI MM component and see what's inside. 

There are two other pci express components in Vivado that will give you direct access to PCI-e streaming interface but you will have to go through the entire pci-express protocol to decode it.

See the docs here.

https://www.xilinx.com/support/documentation/ip_documentation/axi_pcie3/v3_0/pg194-axi-bridge-pcie-gen3.pdf

https://www.xilinx.com/products/intellectual-property/7_series_pci_express_block.html

https://www.xilinx.com/products/intellectual-property/7_series_gen_3_pci_express.html#documentation

 

 

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Observer delk
Observer
1,610 Views
Registered: ‎02-05-2014

Re: PCIe accelerator

Is there any ready driver I could you for to stream data from the PCIe to my core using AXI MM? Alternatively, is there any workaround in order to use the AR56444 driver with the xdma connected to my core (instead of the DDR3 memory) to send/receive data? 

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Scholar hbucher
Scholar
1,606 Views
Registered: ‎03-22-2016

Re: PCIe accelerator

@delk 

Page 86

https://www.xilinx.com/support/documentation/ip_documentation/xdma/v3_0/pg195-pcie-dma.pdf

 

 

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Observer delk
Observer
1,596 Views
Registered: ‎02-05-2014

Re: PCIe accelerator

Correct If I am wrong, in the example design you pinpointed do I break the AXI-ST loopback and insert my core, right?

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Scholar hbucher
Scholar
1,593 Views
Registered: ‎03-22-2016

Re: PCIe accelerator

@delk Correctomondo

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Observer delk
Observer
1,581 Views
Registered: ‎02-05-2014

Re: PCIe accelerator

OK, so BAR0 will translate to my core or BRAM It is not very clear to me how the address space should be. When I use for example dma_to_device to send data, is the mapped address of my core or BRAM the right address I should be sending data to? 

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Scholar hbucher
Scholar
1,520 Views
Registered: ‎03-22-2016

Re: PCIe accelerator

@delk That I am not sure brother. It has been a while I dealt with this PCI-e driver. But there are examples in the code, have a look.

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