07-12-2017 02:56 AM
Hi Xilinx Community,
in my Design I enabled the PL Fabric Clock PL0 in the Processor IP to clock the PL as you can see. Unfortunately the clock is dead so my logic is not working. Is the Clock configuration right?
I also have Problems with tha AXI HPM FPD Interfaces. I cannot read/write on those Interfaces. I am stuck, because this is a very simple Design and nothing is working but it seems to me that the Processor IP Configuration is correct, right?
I use XSDB in Vivado 20164 to download .bit file, execute init.tcl and to download .elf file.
Thanks in advance
07-12-2017 03:10 AM
Could you try using SDK GUI and system debugger and let me know if you have the same results.
07-24-2017 01:46 PM
The PLLs in the PS are configured when a PS software application is loaded, they are not configured by the PL firmware. So, until an application is loaded, the PS clocks will be stopped.
For this reason, I avoid using the PS PLL's whenever possible. Better to generate your PL clocks in the PL.