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PS-PL AXI

Adventurer
Posts: 88
Registered: ‎11-09-2009

PS-PL AXI

Hi,

About PL-PS interconnect.

When using the for example M_AXIGP0 between PL-PS, there is M_AXI_GP0_CLK input in zynq-block.

Can this clock be anything, can I take take FCLK0 from PS and put PLL between and then use this PLL frequency to  M_AXI_GP_CLK ?

 

Can the frequency of this signal also be changed without generating the init_file for PS-side ?

Does it have to be aware of the freq used ?

 

-Tero

 

 

 

 

Teacher
Posts: 4,871
Registered: ‎03-31-2012

Re: PS-PL AXI

@teroki as long as you don't violate the worst case period of the m_axi_gp0_clk PS doesn't need to know how fast it will run and you don't need a new init file for PS when you change it so yes you can take fclk0, pass it through a pll and drive m_axi_gp0_clk with the output. 

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Adventurer
Posts: 88
Registered: ‎11-09-2009

Re: PS-PL AXI

Hi Muzaffer,

Thanks for the answer.

One question though:

Do the PL-side MMCM/PLLs require the reset signal during the start-up ?

My feeling is that they don*t.

 

The clocks are supposed to be stable after the init files,and then after the FPGA configuration, the FCLK_reset is released but PLLs don't need to be reseted. MMCM start-up handles that.

FCLK_reset wouldn't be needed for the PLLs during start-up.

Correct ?

 

 

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Teacher
Posts: 4,871
Registered: ‎03-31-2012

Re: PS-PL AXI

@teroki

 

>> FCLK_reset wouldn't be needed for the PLLs during start-up.

 

that's most probably true. I never use it but it's possible some usage may require it.

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