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Visitor mimmori
Visitor
2,837 Views
Registered: ‎05-14-2014

[Place Design Fail] Route PJTAG to FPGA IO through EMIO via Custom Logic

I am working on a project based on ZYNQ 7Z020.

 

I need to route PJTAG port from EMIO pins to FPGA pins not directly but through a multiplexer. I implemented the logic and all is ok except for TDO signal. I have a fail error during implementation phase.

 

Here the error: [DRC 23-20] Rule violation (REQP-1581) obuf_loaded - OBUFT Zynq_ps_inst/processing_system7_0/inst/PJTAG_OBUFT_TRUE.jtag_obuft_inst pin O drives one or more invalid loads. The loads are: Zynq_pl_inst/jtag_ctrl_inst/r_jtag_ctrl/SYS_conn_jtdo_OBUF_inst_i_1

 

It seems related to OBUFT present in the PS and that I can't pass through any logic. Is it true? If no, how can I realize this function?

 

Regards,

Domenico

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Teacher muzaffer
Teacher
2,810 Views
Registered: ‎03-31-2012

Re: [Place Design Fail] Route PJTAG to FPGA IO through EMIO via Custom Logic

@mimmori you should have an output & a tri-state signal separately from PS and drive the actual tdo pin on PL with an assign which also controls the enable, ie:

 

output tdo;

...

wire tdo = tdo_tri ? 1'bz : tdo_out;

 

In other words you can't take the output of the OBUFT and drive it inside the FPGA. You need to take the inputs of the OBUFT (out & tri), take it through the PL and drive it at the PL IO as shown above.

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Adventurer
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2,789 Views
Registered: ‎05-29-2014

Re: [Place Design Fail] Route PJTAG to FPGA IO through EMIO via Custom Logic

@muzaffer I have the same problem. I found this table on the UG585:

 

pjtag.PNG

 

So it seems that the PJTAG port have 5 signals, with the TDO split into the data and the 3-state control.

But, in the block design (Vivado 2016.6), when I enable the PJTAG, it comes with only 4 signals, and the TDO does not have the 3-state control signal.

So it seems that there is a software limitation in doing what you suggest,

Is there an alternative way to do it, or I'm doing it in the wrong way?

 

regards

Davide

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Visitor mimmori
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2,738 Views
Registered: ‎05-14-2014

Re: [Place Design Fail] Route PJTAG to FPGA IO through EMIO via Custom Logic


@muzaffer wrote:

@mimmori you should have an output & a tri-state signal separately from PS and drive the actual tdo pin on PL with an assign which also controls the enable, ie:

 

output tdo;

...

wire tdo = tdo_tri ? 1'bz : tdo_out;

 

In other words you can't take the output of the OBUFT and drive it inside the FPGA. You need to take the inputs of the OBUFT (out & tri), take it through the PL and drive it at the PL IO as shown above.


@muzaffer I can not take off from block design the input of the OBUFT. I don't konw how to do that.

 

pjtag.PNG

 

Is there a way to bring out the TRI and the INPUT of the OBUFT instead of the output only?

 

 

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