09-02-2015 02:58 AM
I'm working on the power sequencing for a XC7Z030. I've hooked some of the rails up together and have the following sequence. Does this look acceptable? I found the datasheets a little confusing with the info scattered around a bit/
09-25-2015 12:27 AM - edited 09-25-2015 12:41 AM
We recommend to follow power-up and power-down sequence mentioned in page 9 ofXC7Z030 data sheet http://www.xilinx.com/support/documentation/data_sheets/ds191-XC7Z030-XC7Z045-data-sheet.pdf
As per that data sheet
All power supply rails were not shown in your post. Also make sure that PS and PL should have sepearate power regions. So please check as per the above statements and let us know if you still have doubts
09-25-2015 06:36 AM
Hi, shortly after posting I realised I uploaded the wrong diagram.
THe one I was supposed to upload was this one, which as longer gaps between the rails rising.
I've read the power requiements, but its a bit confusing, and I'm trying to save as much space as possible on the power supply.
I know that VCCPAUX, VCCAUX and VCCPLL can be tied together (as stated in Chapter 5 of the Zynq-7000 PCB Design Guide), and also VCCPINT and VCCINT can be tied together (same reference).
Its difficult to understand whats ok, as the first statement states VCCPINT, VCCPAUX and VCCPLL together. And VCCINT, VCCBRAM, VCCAUX, VCCAUX_IO etc in sequence.
Yet another document states I can link VCCINT with VCCPINT, and VCCPAUX with VCCAUX, which makes it impossible to start up in the sequence.