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Visitor imran_123
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1,796 Views
Registered: ‎03-07-2017

Problem with Example Design- Using AXI DMA in polled mode to transfer data to memory

Hello All, I am trying to implement "Example Design- Using AXI DMA in polled mode to transfer data to memory" given at https://www.xilinx.com/support/answers/57561.html , i got the zynq based system in vivado 2016.2 and i upgraded to vivado 2016.4. but i got errors in SDK part 

 

sdk_error.JPG

and also xgpio.h is not available in BSP includes

 

sdk_error1.JPG

 

 please help me to remove the errors

 

thanks 

regards

Imran

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Scholar hbucher
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1,782 Views
Registered: ‎03-22-2016

Re: Problem with Example Design- Using AXI DMA in polled mode to transfer data to memory

@imran_123 

xgpio.h is generated automatically for you - but only if you add a GPIO to your block design.

 

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Visitor imran_123
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Registered: ‎03-07-2017

Re: Problem with Example Design- Using AXI DMA in polled mode to transfer data to memory

Thanks Henry Bucher

 i did what you told me, xgpio.h error is gone but some new error appears.

 

 

../src/helloworld.c:35:21: fatal error: xllfifo.h: No such file or directory
#include "xllfifo.h"
^
compilation terminated.
make: *** [src/helloworld.o] Error 1

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Scholar hbucher
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Registered: ‎03-22-2016

Re: Problem with Example Design- Using AXI DMA in polled mode to transfer data to memory

@imran_123

Same thing. It is only added when you add an AXI Stream Fifo to your board design.

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Visitor imran_123
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Registered: ‎03-07-2017

Re: Problem with Example Design- Using AXI DMA in polled mode to transfer data to memory

it is already there in board design given by this answer record 

https://www.xilinx.com/support/answers/57561.html

polled_bd.JPG

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Scholar hbucher
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Registered: ‎03-22-2016

Re: Problem with Example Design- Using AXI DMA in polled mode to transfer data to memory

@imran_123 That is a "AXI Stream Data FIFO". You need a "AXI-Stream FIFO".

The first is stream-stream. The one you need is memory mapped-stream.

 

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