01-14-2019 09:33 AM
I am a newcomer to embedded development in regards to Xilinx development boards. I followed some FPGA programming tutorials and read documentation regarding the development of VHDL and Verilog, design creation and IP packaging but am currently in need of assistance for a specific development case regarding Ethernet packet processing using the Programmable Logic (PL) and the Zedboard Zynq Evaluation and Development Kit.
I have a few questions that I would like to be verified to progress further in this project:
- Can Ethernet packet information be transferred from the Processing System (PS) to the PL, for the PL to then send results back to the PS for network-based analysis and if so how could this be implemented?
- Could a similar mechanism be introduced for a WiFi controlled USB Driver connected to the USB interface of the Zedboard?
- Should I use the Vivado HLS editor, the Xilinx SDK, or the Vivado IDE to develop such functionality?
01-14-2019 10:41 AM
01-15-2019 10:49 AM
01-15-2019 10:21 PM
01-18-2019 01:38 PM
Certainly and I'm fully aware, I have been practicing and following tutorials using each of the tools in question.
Since this task can be done with any I would plan on using the Vivado HLS in that I have more experience with C programming.
01-20-2019 02:58 AM