05-13-2015 08:42 AM
I'm building a multicore SoC using XPS 14.7 and a Spartan-6 LX150T. My system looks like:
The XPS flow continues with success, I can then build a test C application.The problem I face is that the system_cache and the SDRAM are no longer accessibile from any microblaze core. So the C application can print to UART but cannot access the SDRAM. So the below warnings are REAL and cannot be ignored.
I'm attaching the mhs as well.
Please support on this.
WARNING:EDK:3967 - axi2axi_connector (axi2axi_connector_0) - ADDRESS specified by PARAMETER C_S_AXI_RNG01_BASEADDR is ignored - C:\WS\C5S\2_Castle5_Dev\3_INT_TEMPLATE_QUADCORE__v14.7__\3_INT_TEMPLATE_QUADCORE\INT_TEMPLATE_QUADCORE_MC5\HW\system.mhs line 483 WARNING:EDK:2137 - Peripheral system_cache_0 is not accessible from any processor in the system. Check Bus Interface connections and address parameters. WARNING:EDK:2137 - Peripheral sdram_ddr3 is not accessible from any processor in the system. Check Bus Interface connections and address parameters.
05-13-2015 08:48 AM
what is system_cache IP in your MHS?
the MHS shows SDRAM is at 0x8000_0000 however the cache enabled on both the microblaze processors is at 0x0xA8000000
05-13-2015 09:04 AM
Thanks for your prompt reply,
The address 0x8000_0000 was a typo, I corrected it, Project > Clean all, rebuild >> same warnings.
system_cache enables L2 cache for multicore design. It implements cache coherency for all cores connecting their ACE_DC and ACE_IC microblaze ports.
05-13-2015 10:16 AM
Analyzing the log, I found:
Performing Clock DRCs... Performing Reset DRCs... Overriding system level properties... .. INFO: Setting C_RANGE_CHECK = OFF for axi_interconnect axi_sdram; no DECERR checking will be performed.
C_RANGE_CHECK is ON for other busses. Why is XPS neglecting the address ranges from this bus?
05-13-2015 01:43 PM
Range check is disabled for point to point interconnect designs. There must still be an issue with your Microblaze cache setup.
05-14-2015 02:38 AM
I'm attaching the mhs after typo fix. Can you build a project using the mhs and check what's wrong. I've been reading the data sheets for both microblaze and system cache with no luck till now.
Additionally, I did not find any reference project for multicore microblaze using system_cache.
Please support on this.
05-21-2015 02:00 AM
The root cause of the problem is that EDK is not able to include the DDR in the address map in this case. This means that the LMB automatic address mask calculation (C_MASK) is not able to take the DDR into account. This results in accesses meant for the DDR ending up in LMB instead.
To fix this, the correct address mask has to be assigned manually (see the attached system_fixed.mhs).
After doing this, I have run DDR memory tests correctly on both processors on SP605 (where I also had to change C_MCB_RZQ_LOC and C_MCB_ZIO_LOC).
05-29-2015 05:52 AM
Yes, this warning will remain, because of the EDK address map limitation. However, you should be able to access the DDR correctly.