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Observer mmagdi
Observer
520 Views
Registered: ‎04-25-2018

Send Interrupt from BRAM to PS on Zedboard

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Hello everyone,

I am looking for a turoial or tips on how to send an interrupt from the BRAM (when a value in it changes based on an action from a custom PL) to the PS side on the Zedboard.

All what I found so far are tutorials on interrupts on the Zedboard are concerned more with GPIOs, any advice?
Thanks in advance.

 

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Xilinx Employee
Xilinx Employee
461 Views
Registered: ‎01-09-2019

Re: Send Interrupt from BRAM to PS on Zedboard

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Hello @mmagdi 

This sounds like something that would be best built using some custom IP.  Could you not constantly poll that address in BRAM and on a rising or falling edge change of that memory location send an interrupt to the interrupt port on the Zedboard?  The interrupt can be a simple signal from an FSM so if nothing is special about the interrupt you could have an FSM that does all of that for you.

The FSM shouldn't be too difficult to build: if you have a rising or falling edge on that memory_location, or compare that memory_location with data it had the previous clock sycle, then set a signal interrupt_out to 1 on the next clock edge otherwise if no change occurred set interrupt_out to 0 on all other clock edges.  The reading of the data in BRAM shouldn't be too difficult either, but may be a little more complicated.  You may want to look into the AXI DMA IP or AXI CDMA IP as that will be able to read from BRAM while your PS side is doing other tasks, and then send that data to your FSM to process and check if a change had occurred.

Thanks,
Caleb
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9 Replies
Xilinx Employee
Xilinx Employee
462 Views
Registered: ‎01-09-2019

Re: Send Interrupt from BRAM to PS on Zedboard

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Hello @mmagdi 

This sounds like something that would be best built using some custom IP.  Could you not constantly poll that address in BRAM and on a rising or falling edge change of that memory location send an interrupt to the interrupt port on the Zedboard?  The interrupt can be a simple signal from an FSM so if nothing is special about the interrupt you could have an FSM that does all of that for you.

The FSM shouldn't be too difficult to build: if you have a rising or falling edge on that memory_location, or compare that memory_location with data it had the previous clock sycle, then set a signal interrupt_out to 1 on the next clock edge otherwise if no change occurred set interrupt_out to 0 on all other clock edges.  The reading of the data in BRAM shouldn't be too difficult either, but may be a little more complicated.  You may want to look into the AXI DMA IP or AXI CDMA IP as that will be able to read from BRAM while your PS side is doing other tasks, and then send that data to your FSM to process and check if a change had occurred.

Thanks,
Caleb
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Observer mmagdi
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Registered: ‎04-25-2018

Re: Send Interrupt from BRAM to PS on Zedboard

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Hello @calebd
Thanks a lot for the detailed answer. I will give it a try and see how it goes.

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Scholar vanmierlo
Scholar
417 Views
Registered: ‎06-10-2008

Re: Send Interrupt from BRAM to PS on Zedboard

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If the PL can write to BRAM, can it not also activate the interrupt at the same time? Seems a lot easier to me than trying to follow what happens at the memory location.

You could also catch the write transaction to the specific address on the bus. What interface does the PL use to access the BRAM?

Xilinx Employee
Xilinx Employee
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Registered: ‎01-09-2019

Re: Send Interrupt from BRAM to PS on Zedboard

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@vanmierlo 

I think both of those would also be possibilities.  Probably the first would work best depending on how the design is setup as you could use a SW read to see when the BRAM value changed.

If an AXI interface is used to access the BRAM in the PL, that could also be a trigger.  I feel like using the interface itself may be more difficult than a custom IP that is constantly polling for data from the BRAM, but I haven't done either so I can't say which would be easier.

Thanks,
Caleb
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Scholar vanmierlo
Scholar
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Registered: ‎06-10-2008

Re: Send Interrupt from BRAM to PS on Zedboard

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No, I think a custom IP that is constantly polling the memory location is more difficult, not to mention more resource-intense. You would need one of the two ports of a dual-ported ram to do this. Then you also need one for your PL to write to the ram and another for your CPU to read the ram. Oh wait, didn't I just say there are only two?

Either an AXI interface or the native BRAM port doesn't really matter much. A full AXI can be difficult with incrementing bursts and different transaction ID's. But an AXI-Lite or the native port are pretty straight forward.

AXI-Lite: check awvalid, awready and awaddr and you know when a specific address is written to.

Native: check ena, wea and addra (or b) and you know when a specific address is written to.

But if you can modify the source that is writing the BRAM, then that is the easiest place to modify and generate the interrupt.

 

This whole discussion does make me wonder why you would want this in the first place and if there wasn't a wrong design choice made already. BRAM is not an ideal communication medium if you ask me.

Observer mmagdi
Observer
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Registered: ‎04-25-2018

Re: Send Interrupt from BRAM to PS on Zedboard

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@vanmierloYour hunch is right, it is not the best possible design but rather a working solution that is too late to change now.
I am integrating an open source RISC-V processor with the Zedboard and it is just a learning process, since this kind of IP was not actually designed for that.
I will definetely take a look into the AXI-Lite awvalid, awready and awaddr like you suggested and this should do the trick.

Thanks again!

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Xilinx Employee
Xilinx Employee
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Registered: ‎01-09-2019

Re: Send Interrupt from BRAM to PS on Zedboard

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@vanmierlo 

Wouldn't you need some custom logic to check those values in AXI-Lite?  But yes if you can sniff those values easily that would be pretty easy.  Just trying to visualize how that would be organized and built.  And I also agree this is an interesting design decision, but if needed it shouldn't be too difficult a task to do.

Thanks,
Caleb
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Scholar vanmierlo
Scholar
337 Views
Registered: ‎06-10-2008

Re: Send Interrupt from BRAM to PS on Zedboard

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Yes, of course it requires some custom logic. But isn't that what us fpga designers are supposed to be doing?

How about this:

entity write_detector is
port (
    clk       : in std_logic;
    s_awaddr  : in std_logic_vector(31 downto 0);
    s_awvalid : in std_logic;
    s_awready : out std_logic;
    ... (all those other AXI-Lite signals)
    m_awaddr  : out std_logic_vector(31 downto 0);
    m_awvalid : out std_logic;
    m_awready : in std_logic;
    ... (all those other AXI-Lite signals)
    interrupt : out std_logic
);
end write_detector;

architecture behavior of write_detector is
begin
    m_awaddr <= s_awaddr;
    m_awvalid <= s_awvalid;
    s_awready <= m_awready;
    ... (all those other AXI-Lite signals)

    process begin
        wait until rising_edge(clk);
        if awvalid = '1' and awready = '1' and awaddr = MYSPECIALADDR
        then
            interrupt = '1';
        else
            interrupt = '0';
        endif;
    end process;
end;

Poor this into a packaged IP and you can even place it inline on your Block Design.

Observer mmagdi
Observer
314 Views
Registered: ‎04-25-2018

Re: Send Interrupt from BRAM to PS on Zedboard

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Wow, this is really above and beyond what I expeceted. Thanks a lot for the code, this just made my day a lot easier.
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