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Visitor zeroc00l
Visitor
270 Views
Registered: ‎02-13-2019

Simple AXI counter behaving strangely

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I am trying to create a simple AXI counter IP using a ZC702 evaluation kit.

My verilog for the IP

 

reg [31:0] counter;
    assign count = counter;
    always @( posedge S_AXI_ACLK ) begin
        if ( S_AXI_ARESETN == 1'b0 )  begin
            counter <= 0;
        end else begin
            if (counter < 100) counter <= counter +1;
            else counter <= 0;
        end
    end

I have added an Integrated Logic Analyzer to the design, and I am monitoring the clock and output (count) from the IP. The count keeps on increasing even if it is not a positive edge of the clock, but as per the Verilog code it should only increment on a posedge. Is my verilog incorrect?

Capture.PNG

 

2.PNG

 

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Scholar u4223374
Scholar
241 Views
Registered: ‎04-26-2015

Re: Simple AXI counter behaving strangely

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Are you sure that top signal is actually s00_axi_aclk? Because that doesn't look like a normal clock signal. For a start, it's a 60/40 duty cycle...

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Scholar u4223374
Scholar
242 Views
Registered: ‎04-26-2015

Re: Simple AXI counter behaving strangely

Jump to solution

Are you sure that top signal is actually s00_axi_aclk? Because that doesn't look like a normal clock signal. For a start, it's a 60/40 duty cycle...

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Visitor zeroc00l
Visitor
161 Views
Registered: ‎02-13-2019

Re: Simple AXI counter behaving strangely

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Thanks for pointing that out. That was the problem
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