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Voyager
Voyager
13,583 Views
Registered: ‎05-09-2008

Slave port HP0 on Zynq problem ...

Hi

I have ZC702 board and start to use High Performance 64-bit AXI Slave Port on Zync
device but with some problem.

I have a custom master AXI 64-bit data bus connected to slave part of "axi_interconnect"  
and master part of "axi_interconnect" to slave HP0 port of Zync processor. All
connection, reset and clock seem ok, tool do not report any errors.

High Performace Slave AXI interface HP0 have a default setup with Data Width 64-bit.

I have connected the monitor "Chipscope AXI monitor" to my custom master bus to
analyze the transaction on AXI bus.

Compiling do not report errors.

I have allocate in software a space of 8192 byte, malloc get me address 0x0010C018 for
region. I initiated this region with null char (0x00) and I started the transaction
on AXI bus.

I have capture a transaction on my custom AXI muster :

 

Chipscope.png

AWADDR      : 0x0010C018                      (destination of write, malloc region on software)
WDATA          : 0x471FFF0000000000    (8 bytes for 64-bit bus)

WSTRB         : 0xFF                                     (0b11111111 bit mask all bytes are written)

AWSIZE        : 0x03                                     Burst size. 8 bytes (64-bit wide)
AWBURST   : 0x01                                     Burst type. 01b = INCR - Incrementing address.
AWCACHE   : 0x03                                    Cache type. Fixed to 0011b.
AWLEN         : 0x00                                    Burst length. 0000b = 1 size of transfer.

Remainder signal are fixed to "0"

After this signle write I do not find at address 0x0010C018 the value 0x471FFF0000000000

Why ?

Where can be the problem ?

 

secureasm

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10 Replies
Xilinx Employee
Xilinx Employee
13,572 Views
Registered: ‎02-01-2008

Re: Slave port HP0 on Zynq problem ...

My first guess would be that cache is getting in the way. When you initialize the memory with 0, the cache will hold that value so that when you read with the cpu, you will read cache.

 

A couple of ways to handle this is 1) disable data cache 2) don't do any writes to that memory from the cpu. That way, the first read will pull the data from DDR into cache and therefore should contain your written data.

Voyager
Voyager
13,562 Views
Registered: ‎05-09-2008

Re: Slave port HP0 on Zynq problem ...

Hi,

 

> ... you will read cache.

 

OK, there is the possibility that reads the cache, but also from XMD using MRD commad ?

 

With XMD I read memory directly, right ?

 

Perhaps the problem lies elsewhere. I connected a monitor to the AXI slaveon the HP0 port of Zynq, There are some unexpected surprises.

 

Chipscope Slave.png

(1) We note that the data bus is always zero.

(2) Bitmask of write byte is 0x0F (32 bit) instead of 0xFF (64 bit).

(3) Length of burst write is 0x0F (16 bus write) instead of 0x00 (1 bus write)

(4) The ready signal remain always high ... very strange.

 

The Axi interconnect block have one master and one slave, then the connection should be point-to-point, without any control on the part of the block. But does not appear to be so.

 

Any other ideas ?

 

secureasm

 

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Xilinx Employee
Xilinx Employee
13,548 Views
Registered: ‎02-01-2008

Re: Slave port HP0 on Zynq problem ...

XMD will read a cached value.

 

WDATA always zero, and WSTRB 0x0F tell me either your master isn't doing what it should or the axi interconnect doesn't understand what the master's capabilities are. In XPS, double click on the axi interconnect and verify the master and slave settings for data width. The mpd, of your master, holds the data width info that the interconnect uses. Also, make sure the interconnect is set for AXI4 and not AXILITE. Also, make sure you've setup the HP port for 64bits using the Zynq tab in XPS.

 

You can ignore AWLEN=0x0F because AWLEN is 'sampled' when both READY and VALID are active. At this time, AWLEN=0x00.

 

It's fine for READY to always be high. The HP ports have FIFOs so you would have to saturate the FIFO before the HP port would need to say that it's not ready.

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Voyager
Voyager
13,528 Views
Registered: ‎05-09-2008

Re: Slave port HP0 on Zynq problem ...

Hi johnmcd,

> XMD will read a cached value.

Ok, but why with microblaze I can read and with ARM not ? The cache does not work
in the same way ?

I have done several tests with other cards and I found the problem of  WSTRB, it
remains to update the cache.

The problem is on "axi_interconnect 1.06a".

If I use a Spartan-6 LX150T development board I have the same problem of ZC702,
WSTRB on Memory port is always 0x0F instead of 0xFF for bus of 64-bit.

In my project I have implemented, using System Generator Mcode, a state machine
to write on "AXI master bus" with bus of 64-bit. The project simulates a write
of 188 byte starting from address that user with software pass to pcore. I add
my pcore to ZC702 project without error, the tool does not report errors. I have
check that slave bus from "AXI Interconnet" to "High performace AXI" is 64-bit.

> In XPS, double click on the axi interconnect and verify the master and slave
> settings for data width. The mpd, of your master, holds the data width info
> that the interconnect uses. Also, make sure the interconnect is set for AXI4
> and not AXILITE. Also, make sure you've setup the HP port for 64bits using the
> Zynq tab in XPS.

If you turn on the channel "High performace AXI HPx" default of the selection for
bus is 64-bit but it is not !!!! Move the combo box "32-bit/64-bit" and select
64-bit, otherwise it will have a 32-bit bus. You can check ports
"ports/processing_system7/s_axi_hp0/s_axi_hp0_wdata[63:0]".

In "AXI Interconnet block" on tabs "Ports" I see that bus data master/slave is 64-bit.

To carry out the first tests I inserted a Chipscope AXI monitor on Master port of
my pcore and on a Slave port of "High performance port". On both chipscope block
I have adding the "PARAMETER C_MON_AXI_DATA_WIDTH = 64" in mhs file because Chipscope
do not detect a bus of 64-bit.

If I compile this setup project the "AXI interconnect block" master port to slave
port HP0 is 32-bit, even if in the tab "ports" "ports/processing_system7/s_axi_hp0/s_axi_hp0_wdata[63:0]".
i see 64-bit. After several attempts I have add on MHS file a parameter

PARAMETER C_S_AXI_DATA_WIDTH = 0x00000040000000400000004000000040000000400000004000000040000000400000004000000040000000400000004000000040000000400000004000000040

with this change all work as I expected :

WDATA          : 0x471FFF0000000000    (8 bytes for 64-bit bus)

WSTRB         : 0xFF                                     (0b11111111 bit mask all bytes are written)

 

Chipscope.png

 

Now how to update the region of the cache so that the CPU has valid data ?

 

With use of  "AWCACHE" is possible ?

 

On Spartan-6 LX150T development board no cache problem is present, XMD and "Memory on SDK" is visible change during the AXI writing.

 

secureasm

13,495 Views
Registered: ‎10-08-2012

Re: Slave port HP0 on Zynq problem ...

Hi secureasm

 

I think you do write to DDR but you could read (see) true data!

Bypass CPU cach and read memory directly in XMD by mrd_phy.

 

mrd_phys <address> [num] [w|h|b]                              Cortex A9 Memory Read through AHB AP (default: 'w'ord)

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Newbie gk582
Newbie
13,484 Views
Registered: ‎10-08-2012

Re: Slave port HP0 on Zynq problem ...

I just had the exact same problem last night.

I read this post today and tried "mrd_phys" command and it looks like you are right, the data is written to the DDR correctly.

Do you know how i can force the CPU to read from the DDR and not from cache ?

 

I think i can do it under linux but i'm not sure how to do it in a baremetal setup...

 

Thanks again,

gilad

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Newbie gk582
Newbie
13,479 Views
Registered: ‎10-08-2012

Re: Slave port HP0 on Zynq problem ...

Just tried it under linux using the following very basic code:

 

#include <stdio.h>
#include <stdlib.h>
#include <fcntl.h>
#include <sys/mman.h>

int main()
{

	int memfd;
	volatile int *ddrmem = NULL;

	printf("Hello World\n");

	memfd = open("/dev/mem", O_RDWR | O_SYNC);
	if(memfd == -1)
	{
		printf("Cannot open memory\n");
	}
	printf("Memory Opened\n");


	ddrmem = (int *)mmap(0,0x10, PROT_READ | PROT_WRITE, MAP_SHARED, memfd, 0x20000000);
	if(*ddrmem == -1)
	{
		printf("Cannot map DDR memory\n");
	}
	printf("DDR memory mapped\n");

    printf("DDR value is: %x \n\r", *ddrmem);


    printf("DDR value is: %x \n\r", *ddrmem);


    return 0;
}

 

My PL code writes a single 32bit word (0xdeadbeef) to address 0x20000000 (DDR) when a button is pressed.

I debug it under linux using the basic linux hello world application as explained in UG873 (v14.2 July 27, 2012) Page 43.

I have two printf commands to the same address and i put breakpoints on both lines to see the value before i press the button and after i press it.

 

I run the code until the second printf, press the button on the board and resume running the code.

 

The result i get is:

DDR value is: 484a2044    (just random data i guess....)
DDR value is: deadbeef      (The data written by the FPGA)

 

I still can't figure out how to do the same in baremetal application...

 

Hope it helps...

 

Gilad

 

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Voyager
Voyager
13,476 Views
Registered: ‎05-09-2008

Re: Slave port HP0 on Zynq problem ...

Thanks for suggestion on software part.

 

In Bare Metal for update cache before reading or writing I use this code :

 

Write (CPU write to cache -> command update DDR):

Xil_DCacheFlushRange((unsigned int)pointer, size);

Read (Device write to DDR -> command update cache):

Xil_DCacheInvalidateRange((unsigned int)pointer, size);

and work very well.

 

secureasm

Observer smerkli
Observer
12,738 Views
Registered: ‎03-31-2013

Re: Slave port HP0 on Zynq problem ...

@Secureasm: Thank you so much, that works for me as well. I've been trying to get this to work for ages!

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Adventurer
Adventurer
2,965 Views
Registered: ‎09-02-2010

Re: Slave port HP0 on Zynq problem ...

Hi,

 

I have been having the same problem... however it seems now I have finally managed to solve it... I knew since the begginging that care had to be taken with the caches but I though I had set the memory region attribute's correctly in the mmu_table...

 

Anyway, I just wanted to ask how I should do it if I want to change the mmu translation table's so that the attributes for the whole area of the DDR are such that avoid memory from beeing cached... Inicially I had writen this code, but it turn out it does not work for some reason...

 

ps7_init();
init_platform();

for ( i = 0 ; i < 0x20000000 ; i += 0x100000) {
   Xil_SetTlbAttributes(i, 0x10de6);
}

 

As you can see I was trying to re-write the first 512 entries of the mmu_table (ZedBoard has 512MB) and the value 0x10de6 I worked it out based on the initial found that you can find in standalone's library sources and modified it to try to configure as a "shareable device", you can see it in zynq's technical reference guide page 81...

 

What am I doing wrong?

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