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Visitor afridi990
Visitor
3,343 Views
Registered: ‎12-19-2013

Strange behavious of IP when communicated from PPC

Hi Everyone! 
I am trying to simulate a chemical reaction in FPGA. 
  
My basic FPGA architecure consists of 3 processes: 
  
-- Synchronous Process 
--Purely Synchronous with asynchronous SET or RESET 
IGNITE : PROCESS(clk, reset) 
begin 
IF( reset = '1' ) THEN --Synchronous Reset 
Current_State <= ASSIGN_VARS; 
ELSIF (clk'event AND clk = '1') THEN --Rising edge of Clock 
Current_State <= Next_State; 
END IF; 
END PROCESS IGNITE; 
  
  
CIRCUIT : PROCESS(Current_State, 
-- And all other sensitivity list signals 
) -- include the one read. 
BEGIN 
CASE Current_State IS 
        WHEN ASSIGN_VARS => 
                   -- LONG 3000 lines of code here 
                   -- see the attached file 
END CASE; 
END PROCESS CIRCUIT; 
  
--Purely Synchronous with asynchronous SET or RESET 
INITIALIZE : PROCESS(clk, reset) 
BEGIN 
IF(reset = '1') THEN 
glucose_reg <= zeros27; 
ATP_reg <= zeros27; 
glucose_6_phosphate_reg <= zeros27; 
ADP_reg <= zeros27; 
fructose_6_phosphate_reg <= zeros27; 
fructose_1_6_bisphosphate_reg <= zeros27; 
dihydroxyacetone_phosphate_reg <= zeros27; 
glyceraldehyde_3_phosphate_reg <= zeros27; 
bisphosphoglycerate_1_3_reg <= zeros27; 
phosphoglycerate_3_reg <= zeros27; 
phosphoglycerate_2_reg <= zeros27; 
phosphoenolpyruvate_reg <= zeros27; 
pyruvate_reg <= zeros27; 
Pi_reg <= zeros27; 
H2O_reg <= zeros27; 
NAD_reg <= zeros27; 
NADH_reg <= zeros27; 
H_reg <= zeros27; 
--BRAM 
ADDRESS_A_reg <= zeros10; 
DATA_IN_reg <= zeros27; 
-- 
SAVE_DATA_reg <= zeros10; 
TEMP_reg <= zeros5; 
IN_REACTIONS_reg <= B"0"; 
TEMP_STATE_reg <= ASSIGN_VARS; 
ELSIF(clk'event AND clk = '1') THEN 
glucose_reg <= glucose_sig; 
ATP_reg <= ATP_sig; 
glucose_6_phosphate_reg <= glucose_6_phosphate_sig; 
ADP_reg <= ADP_sig; 
fructose_6_phosphate_reg <= fructose_6_phosphate_sig; 
fructose_1_6_bisphosphate_reg <= fructose_1_6_bisphosphate_sig; 
dihydroxyacetone_phosphate_reg <= dihydroxyacetone_phosphate_sig; 
glyceraldehyde_3_phosphate_reg <= glyceraldehyde_3_phosphate_sig; 
bisphosphoglycerate_1_3_reg <= bisphosphoglycerate_1_3_sig; 
phosphoglycerate_3_reg <= phosphoglycerate_3_sig; 
phosphoglycerate_2_reg <= phosphoglycerate_2_sig; 
phosphoenolpyruvate_reg <= phosphoenolpyruvate_sig; 
pyruvate_reg <= pyruvate_sig; 
Pi_reg <= Pi_sig; 
H2O_reg <= H2O_sig; 
NAD_reg <= NAD_sig; 
NADH_reg <= NADH_sig; 
H_reg <= H_sig; 
--BRAM 
ADDRESS_A_reg <= ADDRESS_A_sig; 
DATA_IN_reg <= DATA_IN_sig; 
-- 
SAVE_DATA_reg <= SAVE_DATA; 
TEMP_reg <= TEMP_sig; 
TEMP_STATE_reg <= TEMP_STATE_sig; 
IN_REACTIONS_reg <= IN_REACTIONS_sig; 
END IF; 
END PROCESS INITIALIZE; 
  
I can communicate with this IP from PPC but in a very strange way. 
  
#include "xmk.h" 
#include "sys/init.h" 
#include "platform.h" 
#include <stdio.h> 
#include <string.h> 
#include "platform.h" 
#include "xparameters.h" 
#include "xbasic_types.h" 
#include "xstatus.h" 
#include "xgpio.h" 
#include "source.h" 
#include <sys/timer.h> 
#include "checkppc6.h" 

#include <stdio.h> 
Xuint32 *baseaddr_p = (Xuint32 *)XPAR_CHECKPPC6_0_BASEADDR; 
int main() 

init_platform(); 
XASSERT_NONVOID(baseaddr_p != XNULL); 
baseaddr = (Xuint32)baseaddr_p; 
CHECKPPC6_mReset(baseaddr); 
CHECKPPC6_mResetReadFIFO(baseaddr); 
CHECKPPC6_mResetWriteFIFO(baseaddr); 
  
CHECKPPC6_mWriteToFIFO(baseaddr, 0, 0xffffffff); // activate signal 
  
DataFPGA = CHECKPPC6_mReadFromFIFO(baseaddr, 0); 
  

  
I donot see the initial value from FPGA IP until I send an empty useless value to IP input (which is CHECKPPC6_mWriteToFIFO(baseaddr, 0, 0xffffffff); // activate signal). In my view a simple software reset (CHECKPPC6_mReset) should have initialized the IP and given me the output value I assign in ASSIGN_VARS case of my IP. 
  
My IP design is such that. IP asks the input of chemical molecules. then perform reaction and wait for ACK signal from PPC to continue with the next round. 
  
But the problems I face are. I have to (CHECKPPC6_mWriteToFIFO(baseaddr, 0, 0xffffffff); // activate signal) for no intuitive reason. Then when I provide ACK signal, IP doesnt move on to start Reaction again untill I provide another dummy input (CHECKPPC6_mWriteToFIFO(baseaddr, 0, 0xffffffff); // activate signal). 
  
I believe next_state doesnot get updated, which is why it happens, can you guys please help me with this and suggest a solution. 
  
please see attached files for more info. 


https://drive.google.com/file/d/0BxVHCJ7JxzSDa3lHb3YxdmhTLTA/edit?usp=sharing 

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2 Replies
Teacher muzaffer
Teacher
3,335 Views
Registered: ‎03-31-2012

Re: Strange behavious of IP when communicated from PPC

did you simulate your vhdl model? just create a simple testbench which includes the top level vhd file and generate the reset signal and see how it behaves.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
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Visitor afridi990
Visitor
3,328 Views
Registered: ‎12-19-2013

Re: Strange behavious of IP when communicated from PPC

Yes, I checked it using testbench, and the behaviour in the testbench is as I expected. Its correct. 

 

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
USE std.textio.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY TestBench IS
END TestBench;

ARCHITECTURE behavior OF TestBench IS 

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT GLYCOLYSIS
PORT(
clk : IN std_logic;
reset : IN std_logic;
INPUT32 : IN std_logic_vector(31 downto 0);
OUTPUT32 : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal Input32 : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal Output32 : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;

--
SIGNAL ADDRESS_A : std_logic_vector(9 DOWNTO 0):= (others => '0');

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: GLYCOLYSIS PORT MAP (
clk => clk,
reset => reset,
INPUT32 => Input32,
OUTPUT32 => Output32
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process clk_process;

--
reset <= '1' after 0 ns, '0' after 20 ns;


process(Output32)
--VARIABLE ADDRESS_A : STD_LOGIC_VECTOR(9 downto 0) := (others => '0');
begin

-- IF (Output32 = B"00000000000000000000000000000000") THEN --EMPTY
-- Input32 <= B"00000000000000000000000000000000";
-- END IF;

IF (Output32(31 DOWNTO 27) = B"00100") THEN --glucose_FPGA
Input32 <= B"00100000000000000000001111111111";
END IF; 

IF (Output32(31 DOWNTO 27) = B"00101") THEN --ATP_FPGA
Input32 <= B"00101000000000000010011100010000";
END IF;

IF (Output32(31 DOWNTO 27) = B"00110") THEN --glucose_6_phosphate_FPGA
Input32 <= B"00110000000000000010011100010000";
END IF;

IF (Output32(31 DOWNTO 27) = B"00111") THEN --ADP_FPGA
Input32 <= B"00111000000000000010011100010000";
END IF;

IF (Output32(31 DOWNTO 27) = B"01000") THEN --fructose_6_phosphate_FPGA
Input32 <= B"01000000000000000010011100010000";
end if;

IF (Output32(31 DOWNTO 27) = B"01001") THEN --fructose_1_6_bisphosphate_FPGA
Input32 <= B"01001000000000000010011100010000";
END IF;

IF (Output32(31 DOWNTO 27) = B"01010") THEN --dihydroxyacetone_phosphate_FPGA
Input32 <= B"01010000000000000010011100010000";
END IF;

IF (Output32(31 DOWNTO 27) = B"01011") THEN --glyceraldehyde_3_phosphate_FPGA
Input32 <= B"01011000000000000010011100010000";
END IF;

IF (Output32(31 DOWNTO 27) = B"01100") THEN --bisphosphoglycerate_1_3_FPGA
Input32 <= B"01100000000000000010011100010000";
END IF;

IF (Output32(31 DOWNTO 27) = B"01101") THEN --phosphoglycerate_3_FPGA
Input32 <= B"01101000000000000010011100010000";
END IF;

IF (Output32(31 DOWNTO 27) = B"01110") THEN --phosphoglycerate_2_FPGA
Input32 <= B"01110000000000000010011100010000";
END IF;

IF (Output32(31 DOWNTO 27) = B"01111") THEN --phosphoenolpyruvate_FPGA
Input32 <= B"01111000000000000010011100010000";
END IF;

IF (Output32(31 DOWNTO 27) = B"10000") THEN --pyruvate_FPGA
Input32 <= B"10000000000000000010011100010000";
END IF;

IF (Output32(31 DOWNTO 27) = B"10001") THEN --Pi_FPGA
Input32 <= B"10001000000000000010011100010000";
END IF;

IF (Output32(31 DOWNTO 27) = B"10010") THEN --H2O_FPGA
Input32 <= B"10010000000000000010011100010000";
END IF;

IF (Output32(31 DOWNTO 27) = B"10011") THEN --NAD_FPGA
Input32 <= B"10011000000000000010011100010000";
END IF;

IF (Output32(31 DOWNTO 27) = B"10100") THEN --NADH_FPGA
Input32 <= B"10100000000000000010011100010000";
END IF;

IF (Output32(31 DOWNTO 27) = B"10101") THEN --H_FPGA
Input32 <= B"10101000000000000010011100010000";
END IF;
--

END PROCESS;
 
END;

 

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