06-04-2019 12:34 PM - edited 06-11-2019 02:05 PM
I'm trying to get ptp in Linux to work for all of the Ethernet ports, and had a few questions about GEM register space and where they are configured.
This is using a xczu2eg part using Vivado 2019.1. I have GEM0, GEM1 & GEM2 all enabled in Vivado. GEM0 is through MIO and GEM1 is through EMIO. After enabling CLKACT in GEM_TSU_REF_CTRL 
# memtool mw -l 0xff5e0100 0x01010600
Then the GEM1 ptp seems to be working and I can see the GEM1 tsu_timer_nsec register incrementing:
# memtool md -l 0xff0c01d4+1 ff0c01d4: 293238e4
But whatever I do, the GEM0 tsu_timer_nsec register doesn't seem to change.
# memtool md -l 0xff0b01d4+1 ff0b01d4: 00000000
Both of the tsu_timer_incr registers seem correct
# memtool md -l 0xFF0b01dc+1 ff0b01dc: 00000004 . # memtool md -l 0xFF0c01dc+1 ff0c01dc: 00000004
So my first question is where are the ptp registers supposed to be configured: fsbl, Linux or somewhere else? (I am rebuilding fsbl & pmufw when making Vivado changes). Second, what else could be missing if the GEM1 timer is incrementing, but not the GEM0 one?
One other difference is that because GEM1 is EMIO I have hte emio_enet1_tsu_inc_ctrl[1:0] set to 11 in the block diagram, is there something comparable for GEM0 through MIO?
Thanks in advance for any help.
 memtool is a convenient Linux tool for reading and writing memory mapped register space from the command line.
07-29-2019 08:34 PM
08-13-2019 01:45 PM
I can see GEM2 counting as well now, but sill not GEM0.
# memtool md -l 0xff0d01d4+1 ff0d01d4: 11565b2b
What would be helpful from Xilinx is some additional information about what is needed for timer register to actually start counting and where that configuration is supposeds to be done (fsbl, Linux, etc... ). There is not enough information on the register description page.
08-13-2019 05:47 PM