UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor giovanig
Visitor
1,448 Views
Registered: ‎03-12-2018

Transfer data from PL to PS on ZCU102

Hello,

 

I have a DMA block on the PL side. I would like to use it to access and transfer data from the PL to PS, or to transfer data from PS-OCM to PS-DRAM. I have inserted a slave HPC port on the zynq and connected it to the AXI SMC. A screenshot of the design is attached.

 

The DMA works when I access the PL-side (BRAM or PL-DRAM), but it does not work when I access the PS-side. I get a DMA decode error whenever I access the DRAM or OCM memories. The address mapping of the design is also attached. I am running Linux on the PS.

 

Am I missing something in the design? 

 

Best regards,

Giovani

dma_design.png
dma_address_mapping.png
0 Kudos
11 Replies
Explorer
Explorer
1,407 Views
Registered: ‎01-09-2012

Re: Transfer data from PL to PS on ZCU102

@giovanig

 

I did something similar to check the DDR4 SDRAM performance like in https://forums.xilinx.com/t5/Embedded-Boot-and-Configuration/ZYNQMP-configuration-for-access-PS-DDR-from-PL/m-p/831752#M231

Question to you: Are you aware that the PS is using AXI V3 and in PL we commonly use AXI V4?

 

Cheers

Goran

0 Kudos
Visitor giovanig
Visitor
1,402 Views
Registered: ‎03-12-2018

Re: Transfer data from PL to PS on ZCU102

@gmarinkovic

 

Thanks for pointing out your topic. It seems related, but I did not catch the error. 

 

Are the differences between AXI V3 and V4 not handled by the AXI smart connect? Should I change it to another block?

0 Kudos
Explorer
Explorer
1,396 Views
Registered: ‎01-09-2012

Re: Transfer data from PL to PS on ZCU102

@giovanig

 

The point is that AXI V3 burst are 16 beats long and AXI V4 up to 256 beats long... Hence, to see if this is your problem try to restrict your DMA engine to 16 beats and see what happens.

 

 

Cheers

Goran

0 Kudos
Visitor giovanig
Visitor
1,394 Views
Registered: ‎03-12-2018

Re: Transfer data from PL to PS on ZCU102

@gmarinkovic

 

The current configuration in the DMA block is max burst size of 8 for the reading channel and 16 for the writing channel. So it should not be the problem I believe.

 

Address width is 64 bits, memory map data width and stream data width are also 64 bits. Unaligned transfers is enabled, but micro DMA and scatter gather are disabled.

0 Kudos
Highlighted
Explorer
Explorer
1,388 Views
Registered: ‎01-09-2012

Re: Transfer data from PL to PS on ZCU102

@giovanig

 

The next step would be to see how the AXI communication proceeds. Can you add an ILA AXI bus analyzer to the connection to  PS and have a look what you see? Is the address acknowledged and does the data stream as you configured/expect?

 

Cheers

Goran

0 Kudos
Visitor giovanig
Visitor
1,370 Views
Registered: ‎03-12-2018

Re: Transfer data from PL to PS on ZCU102

@gmarinkovic

 

Ok, I will try that.


In the meantime, I changed the slave port on Zynq from HPC to ACP and got a different error. Instead of the DMA decode error, this time I got a DMASlveErr:

 

DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.

 

Which means that the addresses to access the PS-side memories are correct. However, why DMA may issue a slave error?

0 Kudos
Explorer
Explorer
1,262 Views
Registered: ‎01-09-2012

Re: Transfer data from PL to PS on ZCU102

@giovanig

 

Any news?

 

Cheers

Goran

0 Kudos
Visitor giovanig
Visitor
1,254 Views
Registered: ‎03-12-2018

Re: Transfer data from PL to PS on ZCU102

@gmarinkovic

 

I changed the HPC port to HP and it partially worked. It was able to transfer data from PS DRAM to PL side and vice-versa. However, when PS-side OCM is involved, there is either a freezing on Linux or wrong values are transferred:

 

PS DRAM to OCM - freezes

PL DRAM to OCM - freezes

BRAM to OCM - freezes

OCM to BRAM - did not freeze but it has copied wrong values

OCM to PL DRAM - did not freeze but it has copied wrong values

OCM to PS DRAM - did not freeze but it has copied wrong values

0 Kudos
Explorer
Explorer
1,142 Views
Registered: ‎01-09-2012

Re: Transfer data from PL to PS on ZCU102

@giovanig

Fine... but did you check it with the AXI ILA core as proposed?

Cheers
Goran

0 Kudos
Visitor giovanig
Visitor
738 Views
Registered: ‎03-12-2018

Re: Transfer data from PL to PS on ZCU102

No, I haven't check with AXI ILA. 

0 Kudos
Explorer
Explorer
715 Views
Registered: ‎01-09-2012

Re: Transfer data from PL to PS on ZCU102

The AXI ILA is my preferred tool for such problems plus for checking the efficiency of transfers. Simply do it and you will see a lot more.

0 Kudos