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Explorer
Explorer
2,930 Views
Registered: ‎03-26-2010

US+ MIO ports not shown in Vivado IPI?

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Hi all,

 

Saw something unexpected when cracking open my first Vivado MPSoC Ultrascale+ ZCU102 design: the port of MIO pins that's always been there for Zynq7000 is gone... Seems  that US+ has 78 MIO pins, but there's no port for them shown on the Vivado BD symbol. The MIO pins also don't show up at the hierarchy level and aren't part of the VHDL/Verilog symbol for the Zynq. It's as if MIO is completely missing from the Vivado HDL level since it's not something that can be changed anyway.

 

Is this really how it is or am I missing a setting to enable turning on of the MIO?

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Xilinx Employee
Xilinx Employee
5,530 Views
Registered: ‎08-02-2007

Re: US+ MIO ports not shown in Vivado IPI?

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hi,

 

this is an expected behavior. the MIO ports are not shown as the ports are fixed.

 

are you expecting that the GUI functionality be the same as Zynq-7000 or is there any issue that you are seeing here?

 

--hs

 

 

 

 

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2 Replies
Xilinx Employee
Xilinx Employee
5,531 Views
Registered: ‎08-02-2007

Re: US+ MIO ports not shown in Vivado IPI?

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hi,

 

this is an expected behavior. the MIO ports are not shown as the ports are fixed.

 

are you expecting that the GUI functionality be the same as Zynq-7000 or is there any issue that you are seeing here?

 

--hs

 

 

 

 

----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
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Explorer
Explorer
2,854 Views
Registered: ‎03-26-2010

Re: US+ MIO ports not shown in Vivado IPI?

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No issues yet per se, was just migrating a design over from the 7045, and noticed this break my scripts. Thought it was odd that I couldn't find this documented anywhere.

 

In any case, if this is expected, then everything is working for now.

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