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Observer tk_stoeber
Observer
4,174 Views
Registered: ‎12-04-2013

Using Zynq XADC - Constraints in Vivado

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Hey everyone,

 

I want to find out if the XADC on the Zynq SoC meets our demands. My Hardware is a Zedboard and I want to sample the channels VP/VN, VAUX[0] and VAUX[8] which I connected with the XADC Header.

 

In Vivado 2013.3 I added the "XADC Wizard" IP and configured it with AXI4Lite, Continous Mode, Channel Sequencing. I made the input channels "extern".


When trying to generate the bitstream I get the following error:

 

[Drc 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 4 out of 27 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: Vaux0_v_n, Vaux0_v_p, Vaux8_v_n, Vaux8_v_p.

 

What I/O Constraints do I have to set to get the XADC IP working?

 

 

Trying to find the solution I read some lines in the I/O and Clock Planning tutorial (ug935). I don't find the "I/O Design" and the "I/O Plannung" tools in my Vivado project. (Only a small Project with the zedboard Hardware)

Where do i find  the I/O Planning and Design windows?

 


I hope some can help me out. I'm only a beginner with Vivado.

 

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Xilinx Employee
Xilinx Employee
5,340 Views
Registered: ‎09-20-2012

Re: Using Zynq XADC - Constraints in Vivado

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Hi,

 

Check this http://www.xilinx.com/support/answers/51818.html

 

Specify the IO standards as mentioned in the article.

 

To see "IO planning" view, open either elaborated/synthesized design  and in the drop down at top, you can select IO planning as below.

 

Capture.PNG

 

Thanks,

Deepika.

 

Thanks,
Deepika.
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Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
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2 Replies
Community Manager
Community Manager
4,164 Views
Registered: ‎06-14-2012

Re: Using Zynq XADC - Constraints in Vivado

Jump to solution
0 Kudos
Xilinx Employee
Xilinx Employee
5,341 Views
Registered: ‎09-20-2012

Re: Using Zynq XADC - Constraints in Vivado

Jump to solution

Hi,

 

Check this http://www.xilinx.com/support/answers/51818.html

 

Specify the IO standards as mentioned in the article.

 

To see "IO planning" view, open either elaborated/synthesized design  and in the drop down at top, you can select IO planning as below.

 

Capture.PNG

 

Thanks,

Deepika.

 

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
0 Kudos