UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Participant jamsoft
Participant
1,550 Views
Registered: ‎11-22-2016

VDMA & logicvc & UART

Jump to solution

Hello all,

 

I have a custom Zynq board loaded by design with the VDMA, logicvc (for HDMI output) and Linux working.

 

Currently, the hdmi output is from the Linux X output (logicvc framebuffer).

 

I have the following questions:

 

1) Can the VDMA read from one framebuffer address and write its output to another framebuffer?

2) Is it possible to port the VDMA output framebuffer as a video input source for logicvc?

3) It it possible to use two logicvc layers simultaneously as mixed signal for one hdmi output? (E.g. to have the linux output as a main layer and VDMA output as some smaller window on the screen)

4) Is the Light UART IP able to transmitt data by some non-standard baudrates, e.g. 100000 bps (instead of 115200 bps, for example)

5) Can the Xilinx TPG (Test pattern generator) work without the video input as the standalone pattern generator connected as the image (pattern) source for the VDMA and following image processing or it has to be a part of complete video chain? 

 

Please, please, please, don't advert me to the reference designs as no one of them is designed for my custom board and there are very often to complex to understand it easily. For example, I have tried to understand the design for ZC702 that uses 2 VDMAs, logicvc, etc. but still I do not understand how the VDMA-Sobel-hdmi output works even I read the manual a tousand times... I am a beginner and it is really not easy to understand it from those designs. Thank you...

 

Thank you for your replies and advices.     

 

Jirka

Kindly note: please mark the Answer as "Accept as solution" if information provided is helpful and/or give Kudos to a post. Thank you!
0 Kudos
1 Solution

Accepted Solutions
Highlighted
Adventurer
Adventurer
2,626 Views
Registered: ‎02-14-2014

Re: VDMA & logicvc & UART

Jump to solution

1)  Yes, a VDMA with its stream output connected back to the stream input will do this.   Straight DMA blocks can do this too.  The input and output addresses and most of the control registers are independent across the two sides.  Also look at the CDMA built in DMA engine.

 

2) Yes, if the pixel format, sizes, row stride and multi-buffering offset match how the logiCVC is configured.

 

3) Yes, up to 5 layers mixed. See the enable, size and position registers for each layer to make one of them a smaller window.  

 

5) Yes, TPGs can work standalone and will then generate pixels as fast or slow as the downstream block accepts them.

 

 

There isn't really any easier answer or better documentation than to look at the reference designs... because they're distributed as source just try either porting them to your board or building up your own design by copying parts.  Copy each stage then test that you're getting the right thing in the framebuffers - in the process of figuring out how to test each framebuffer stage you'll figure out how each stage works.

 

 

2 Replies
Highlighted
Adventurer
Adventurer
2,627 Views
Registered: ‎02-14-2014

Re: VDMA & logicvc & UART

Jump to solution

1)  Yes, a VDMA with its stream output connected back to the stream input will do this.   Straight DMA blocks can do this too.  The input and output addresses and most of the control registers are independent across the two sides.  Also look at the CDMA built in DMA engine.

 

2) Yes, if the pixel format, sizes, row stride and multi-buffering offset match how the logiCVC is configured.

 

3) Yes, up to 5 layers mixed. See the enable, size and position registers for each layer to make one of them a smaller window.  

 

5) Yes, TPGs can work standalone and will then generate pixels as fast or slow as the downstream block accepts them.

 

 

There isn't really any easier answer or better documentation than to look at the reference designs... because they're distributed as source just try either porting them to your board or building up your own design by copying parts.  Copy each stage then test that you're getting the right thing in the framebuffers - in the process of figuring out how to test each framebuffer stage you'll figure out how each stage works.

 

 

Participant jamsoft
Participant
1,411 Views
Registered: ‎11-22-2016

Re: VDMA & logicvc & UART

Jump to solution

Thank you for your answer. It was helpful for me.

 

But, I do not fully agree wit your opinion about reference designs... They are made for many different Vivado versions so you have to install more of them and very often they are not really current. For example, you can find reference designs for some IPs but some of them are still made for the ISE or Vivado 2013.x versions incompatible with 2017.2. So, it is much space consuming to have all the Vivado versions installed and also time consuming to port everything to a custom board and understand how the design things really works. If you are not using Zedboard or other well-known evaluation boards it is really not so easy...

Moreover, the examples come with drivers/software for particular Linux Kernel version (Petalinux) and if you need to use some other version/distro (e.g. Linaro) then you spent a much time to get things working as well. Additionally, sometimes it is really impossible as test applications comes in binary form without source code so again, if you are using different Linux/Kernel version you are in trouble and you have to install particular version of the Linux Kernel. Example - often discussed USB drivers incompatibility between the kernels 3.x and 4.x., etc.  

 

That is why I thing that to ask someone who knows on the forum is a faster way to get solution, mostly for a beginner as I am :-)

 

It does not mean that at first step I am not looking for reference designs - I try to use them as well if possible...

 

Thank you for your reply once more and have a nice day!

 

Jirka

 

 

     

Kindly note: please mark the Answer as "Accept as solution" if information provided is helpful and/or give Kudos to a post. Thank you!
0 Kudos