12-06-2018 05:07 AM
We are using Virtex 7 (XC7vx585t-1ffg1761i) in our board to build microblaze processor.In that, we are facing an issue with reset.
Whenever we are using the FPGA code which uses the internal pll lock as reset , the processor boots up and ethernet pings.
If we are using an external reset(connected to a switch on board) , the processor able to boot up and ethernet ping didn't happen
Could you suggest a solution??
12-06-2018 06:10 AM
Is this on Linux?
if you bring the link down, and back up again (basically re-probing the driver), does this work. It might be a auto-neg issue?
12-06-2018 09:10 PM
Thanks for your reply . No, it was not on linux, we are using Windows. It will be a autonegotiation issue( link is up using bit file but not on bin file), Can you suggest how to fix this issue?