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6,260 Views
Registered: ‎08-25-2015

XADC DRP reading code issue

Hi,

 

I am working on XADC and my target is to check only 2nd channel AUX input.

I am using DRP port.

so my configuartion for ADC  is 

 

DRP (yes)

AXI (no)

Single channel (yes)

Averaging (no)

extrenal mux (no)

 

I am checking DRP signals on one my code.

Here it is some routine to check 12 H register for 2nd AUX channel.

in My code AXI connectivity is given.

xadc_present is the register what I am taking input in that.

 

 

--###################################################
--Logic to transmit/receive data to/from XADC IP

NEXT_STATE_DECODE: process (dclk_bufg, s00_axi_aresetn)
begin
if (s00_axi_aresetn = '0') then
state <= init_read;
xadc_present <= X"00000000";
elsif (dclk_bufg'event and dclk_bufg = '1') then
case (state) is

when init_read =>
daddr <= "0010010";--12H (2nd channel address)
den <= "10";
dwe <= "00"; -- performing read
state <= read_waitdrdy;--read_xadc_present;

when read_waitdrdy =>
if eoc_out = '1' then
state <= xadc_present_waitdrdy;
den <= "10";
dwe <= "00"; -- performing read
else
state <= read_waitdrdy;
den <= den;
dwe <= dwe;
end if;



when xadc_present_waitdrdy =>
if drdy = '1' then
xadc_present(15 downto 0) <= do_drp;
den <= den;
dwe <= dwe;
state <= read_waitdrdy;--read_xadc_present;
else
den <= "0" & den(1) ;
dwe <= "0" & dwe(1) ;
state <= xadc_present_waitdrdy;
end if;



end case;
end if;
end process;

 

#########################################################

 

Can anybody help me in this.Is there anything I am missing?

 

Thanks in adavance.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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4 Replies
Xilinx Employee
Xilinx Employee
6,255 Views
Registered: ‎08-01-2008

Re: XADC DRP reading code issue

Running the Testcase:
 
Unzip the Project from the Attachment. 
There is no need to connect anything to the board. 
 
Connect to the board via the Vivado Hardware session. 
 
Program the board with the bitfile. 
You will see the VIO core and the ILA core in the HW session. 
 
Trigger the ILA immediately:
The ILA captures state of the signals mentioned above. 
You should see that the Channel is changing and that the EOS/EOC signals are toggling. 
The Busy signal will also be active. 
 
Reading a conversion result / status register / control register:
 
To read back a register you need to set the Address on DADDR in the VIO. 
Then you need to set start_rd to 1. 
There are two flip-flops that will one shot this so that only one read is done. 
You can set the ILA to trigger on the DEN rising edge. 
You should see the read data appear on the ILA console. 
 
Writing to the DRP interface
 
In this case you need to set the DADDR and DIN on the VIO core. 
You then need to start a write by setting start_wr high. 
In this case you can trigger off DRDY and see the write happen. 
 
The register map and descriptions for all the XADC configuration/status registers is on page 34 of UG480

 

Thanks and Regards
Balkrishan
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6,245 Views
Registered: ‎08-25-2015

Re: XADC DRP reading code issue

Hi,

 

Thanks a lot for response.I was compiling this and I got some typical error.

Opt design error.

I am using Zynq 7000 -2 FBG 676 device and vivado 13.4.

 

 

Does this ILA and VIO work with Zynq?

 

 

Thanks 

 

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6,227 Views
Registered: ‎08-25-2015

Re: XADC DRP reading code issue

Hi,

 

My problem is 60% solved with sequncer mode.I am reading values of temperature,VAUX,VCCINT along woth Aux analog (0 to 3) channels.

I am getting variations evrytime in other channels (temperature and voltages) except aux analog channel.Which is my requirement to b read.

All states for code in one process written so there is no issue of clock and reset.

Is there any other settings to be done in XADC for this?

 

 

Thanks

 

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Moderator
Moderator
6,219 Views
Registered: ‎07-31-2012

Re: XADC DRP reading code issue

Hi,

 

Yes, you can make use of ILA and VIO cores in Vivado.

 

Regards

Praveen


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