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12,170 Views
Registered: ‎12-30-2008

ZC702: Xil_In32() function hanging for ip cores instantiated on the PL side

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Hi,

     I am trying to troubleshoot why the Xil_In32() function hangs on the ZC702 platform, for ip cores instantiated on the PL side.

 

I created a simple hardware project using PlanAhead 14.3 and XPS 14.3, and added an axi_gpio instance.

 

In my SDK project, the main.c file looks like this:

 

/*
 * main.c: gpio and timer test application
 */

#include <stdio.h>
#include "platform.h"
#include "xparameters.h"
#include "xstatus.h"

#include "xil_exception.h"
#include "xil_io.h"
#include "xil_types.h"

#include "xgpio.h"


int main()
{
    // Local variables.
    u32 RegisterAddress;
    u32 Reg32Value;
    XStatus status;

    // Instance variables.
    static XGpio gpio_0_instance;

    // Initialize the platform.
    init_platform();

    print("ZC702 - GPIO and Timer Test Application\n\r");

    // Step 01 : AXI GPIO initialization
    status = XGpio_Initialize(&gpio_0_instance,XPAR_AXI_GPIO_0_DEVICE_ID);
    if(XST_SUCCESS != status)
    {
    	xil_printf("Error: Failed to initialize GPIO, status code = %d\n\r", status);
    }
    else
    {
    	xil_printf("Success: Initialized GPIO, status code = %d\n\r", status);
    }

	// Probe the GPIO
	xil_printf("Attempting to read GPIO\n\r");
	RegisterAddress = XPAR_AXI_GPIO_0_BASEADDR + 0x0;
	Reg32Value = Xil_In32(RegisterAddress);
	xil_printf("Finished reading GPIO register\n\r");
	xil_printf("Xil_In32: GPIO register at address %x, value = %x\n\r", RegisterAddress, Reg32Value);

    // Cleanup the platform.
    cleanup_platform();

    return 0;
}

But in the output, it hangs at Xil_In32() as shown below:

 

ZC702 - GPIO and Timer Test Application
Initialize GPIO, status code = 0
Attempting to read GPIO

It doesn't display a "Finished reading GPIO register" message, as it should if the Xil_In32() function had returned.

 

Elvis Dowson

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13,329 Views
Registered: ‎12-30-2008

Re: ZC702: Xil_In32() function hanging for ip cores instantiated on the PL side

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Hi,

       Thank you very much for your help!

 

Running the init_user command worked, it enabled the level shifters and I was able to execute the program via XMD and the Platform Cable USB II JTAG probe.

 

BTW, where is init_user defined? I couldn't find it when I searched my eclipse workspace.

 

Here is the xmd_top.tcl file:

 

set fsbl_message "Setting FSBL"
set app_message  "Downloading application"

#Download Bitstream (make sure board is in JTAG mode)
fpga -debugdevice devicenr 2 -f system.bit

#Connect To Processor
connect arm hw

#Reset The PS and Fabric
rst

#Initialize the PS
puts "$fsbl_message"
source ps7_init.tcl
ps7_init
init_user

#Download Software Application
puts "$app_message"
dow axi_gpio_timer_test_application.elf

#Run the application
run

#Disconnect from XMD
disconnect 64

 

Here is the output  from the console running on the host:

 

$ xmd -tcl xmd_top.tcl
Xilinx Microprocessor Debugger (XMD) Engine
Xilinx EDK 14.3 Build EDK_P.40xd
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.
Executing user script : xmd_top.tcl
Programming Bitstream -- system.bit
Fpga Programming Progress ............10.........20.........30.........40.........50.........60.........70.........80.........90........Done
Successfully downloaded bit file.

JTAG chain configuration
--------------------------------------------------
Device   ID Code        IR Length    Part Name
 1       4ba00477           4        Cortex-A9
 2       03727093           6        XC7Z020


JTAG chain configuration
--------------------------------------------------
Device   ID Code        IR Length    Part Name
 1       4ba00477           4        Cortex-A9
 2       03727093           6        XC7Z020

CortexA9 Processor Configuration
-------------------------------------
Version.............................0x00000003
User ID.............................0x00000000
No of PC Breakpoints................6
No of Addr/Data Watchpoints.........1

Connected to "arm" target. id = 64
Starting GDB server for "arm" target (id = 64) at TCP port no 1234
Processor stopped

Target reset successfully

Processor stopped

System reset successfully
Setting FSBL
Info:  Enabling level shifters and clearing fabric port resets
Downloading application
Downloading Program -- axi_gpio_timer_test_application.elf
	section, .text: 0x00100000-0x00102727
	section, .init: 0x00102728-0x0010273f
	section, .fini: 0x00102740-0x00102757
	section, .rodata: 0x00102758-0x00102a67
	section, .data: 0x00102a68-0x00103c5b
	section, .eh_frame: 0x00103c5c-0x00103c5f
	section, .bss: 0x00103c60-0x00103ccb
	section, .mmu_tbl: 0x00103ccc-0x0010bfff
	section, .init_array: 0x0010c000-0x0010c007
	section, .fini_array: 0x0010c008-0x0010c00b
	section, .heap: 0x0010c00c-0x0010e00f
	section, .stack: 0x0010e010-0x00112c0f
Setting PC with Program Start Address 0x00100000
Processor started. Type "stop" to stop processor

RUNNING> Disconnected from Target 64

Disconnected from Target 352

 

And here is the output from the ZC702 terminal:

 

ZC702 - GPIO and Timer Test Application
Success: Initialized GPIO, status code = 0
Attempting to set GPIO SW5 data direction
Finished setting GPIO SW5 data direction                                        
SW5 push button pressed                                                         
Press 0 to exit the application, any other key to continue                      
Attempting to read GPIO SW5 base address                                        
Finished reading GPIO SW5 base address                                          
Xil_In32: GPIO SW5 register at address 41200000, value = 0

 

Elvis Dowson

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17 Replies
Scholar norman_wong
Scholar
12,160 Views
Registered: ‎05-28-2012

Re: ZC702: Xil_In32() function hanging for ip cores instantiated on the PL side

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I've had similiar problems with memory mapped PL modules. Check the translation tables to see if that memory range has been configured for read/write access. In the FSBL, it's an assembler file called translation_table.s. Sometimes, certain memory ranges just plain don't work. Try moving to a different memory range.

 

 

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12,151 Views
Registered: ‎12-30-2008

Re: ZC702: Xil_In32() function hanging for ip cores instantiated on the PL side

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Hi,

     The translation_table.s file is in part of the bsp, and not the fsbl. I located it in zc702_standalone_bsp/ps7_cortexa9_0/libsrc/standalone_v3_06_a/src/ folder.

 

I've reverted to using standalone v3.06a, instead of v3.07a, since calls to SYNCHRONIZE_IO were missing in the Xil_In32() and Xil_Out32() functions with v3.07a, and I thought I'd try with the older  v3.06a vesion. FYI, I faced the same problem with v3.07a

 

My axi_gpio peripheral is located at the following base address, taken from xparameters.h

 

/* Definitions for peripheral AXI_GPIO_0 */
#define XPAR_AXI_GPIO_0_BASEADDR 0x41200000
#define XPAR_AXI_GPIO_0_HIGHADDR 0x4120FFFF

My translation_table.s file looks like this, for the memory range:

 

******************************************************************************/
	.globl  MMUTable

	.section .mmu_tbl,"aS"

MMUTable:
	/* Each table entry occupies one 32-bit word and there are
	 * 4096 entries, so the entire table takes up 16KB.
	 * Each entry covers a 1MB section.
	 */

.set SECT, 0

.rept	0x0400			/* 0x00000000 - 0x3fffffff (DDR Cacheable) */
.word	SECT + 0x15de6		/* S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 */
.set	SECT, SECT+0x100000
.endr

.rept	0x0400			/* 0x40000000 - 0x7fffffff (FPGA slave0) */
.word	SECT + 0xc02		/* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b0 */
.set	SECT, SECT+0x100000
.endr

.rept	0x0400			/* 0x80000000 - 0xbfffffff (FPGA slave1) */
.word	SECT + 0xc02		/* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b0 */
.set	SECT, SECT+0x100000
.endr

 

The comments seems to indiate that the memory address range 0x40000000 to 0x7fffffff is covered.

 

But I need to double check the settings, after looking up the ARMv7-A Architecture Reference Manual:

 

S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b0

 

Elvis Dowson

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12,145 Views
Registered: ‎12-30-2008

Re: ZC702: Xil_In32() function hanging for ip cores instantiated on the PL side

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Hi,

      I configured the entries in translation_table.s, to configure the peripherals as both a non-shareable device, and shareable device, but I still could not access the peripheral device registers

 

code snippet for non-shareable device:

.rept	0x0400			/* 0x40000000 - 0x7fffffff (FPGA slave0) */
.word	SECT + 0x2c02		/* S=b0 TEX=b010 AP=b11, Domain=b0, C=b0, B=b0 */
.set	SECT, SECT+0x100000
.endr

.rept	0x0400			/* 0x80000000 - 0xbfffffff (FPGA slave1) */
.word	SECT + 0x2c02		/* S=b0 TEX=b010 AP=b11, Domain=b0, C=b0, B=b0 */
.set	SECT, SECT+0x100000
.endr

 

code snippet for shareable device:

.rept	0x0400			/* 0x40000000 - 0x7fffffff (FPGA slave0) */
.word	SECT + 0xc06		/* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
.set	SECT, SECT+0x100000
.endr

.rept	0x0400			/* 0x80000000 - 0xbfffffff (FPGA slave1) */
.word	SECT + 0xc06		/* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
.set	SECT, SECT+0x100000
.endr

 

I've got the Xilinx Platform Cable USB II connected to the ZC702 JTAG port. I can read data from the DDR3 memory, but I'm unable to read the axi_gpio registers using XMD:

 

XMD% mrd 0x00001000 0x10
    1000:   E54B3005
    1004:   EA00001A
    1008:   E51B300C
    100C:   E283300B
    1010:   E5D33000
    1014:   E2033008
    1018:   E3530000
    101C:   1A000008
    1020:   E51B3018
    1024:   E5933018
    1028:   E51B000C
    102C:   E1A01003
    1030:   E3A0200B
    1034:   EBFFFDBB
    1038:   E1A03000
    103C:   E3530000

XMD% mrd 0x41200000 0xa 
ERROR: Cannot Read from target

 

Any other suggestions as to why this might be happening?

 

I tried this with both standalone v3.06a and v3.07a, and I'm unable to directly read or write to the device registers on the PL side.

 

Elvis Dowson

 

 

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12,134 Views
Registered: ‎12-30-2008

Re: ZC702: Xil_In32() function hanging for ip cores instantiated on the PL side

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I also tried running the EDK 14.2 design tutorial files, which also uses the axi_gpio and has a pre-buit bitstream file

 

http://www.xilinx.com/training/embedded/embedded-design-tutorials.htm

 

I imported the basic_design_zynq_hw_exerciser files, and I get the same results, it hangs.

 

I use an xmd.tcl file to download to the target. Can anyone tell me if there is there is something wrong with my XMD commands:

set myvar "Setting FSBL"

#Download Bitstream (make sure board is in JTAG mode)
fpga -debugdevice devicenr 2 -f basic_design_zynq_top.bit

#Connect To Processor
connect arm hw

#Reset The PS and Fabric
rst

#Download FSBL
dow zynq_fsbl.elf

#Run FSBL
run

puts "$myvar"

#Stop Processor
stop

#Download Software Application
dow basic_design_zynq_hw_exerciser.elf

run

#Disconnect from XMD
disconnect 64

 

Because the hw project was created for ISE 14.2, and I'm using ISE 14.3, I used a zynq_fsbl created using ISE 14.3, but use the pre-built bitstream and regenerated the bsp and projects as outlined in the EDK tutorial.

 

Same result, the system hangs. I can't help but think I'm over looking something very basic.

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Scholar norman_wong
Scholar
12,120 Views
Registered: ‎05-28-2012

Re: ZC702: Xil_In32() function hanging for ip cores instantiated on the PL side

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With my limited experience, the location of the AXI GPIO IP was customizable. Perhaps the address in xparameters.h and the bitstream are different.

 

I haven't used XMD to any extent. The command "rst" clears the fabric? That means it clears the FPGA? The FSBL might clear and program the FGPA as well. The application is loaded afterwards.

 

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12,117 Views
Registered: ‎12-30-2008

Re: ZC702: Xil_In32() function hanging for ip cores instantiated on the PL side

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Hi Norman,

                     The address range for the axi_gpio instance is within the memory range defined in the translation table. When I used the pre-defined bitstream, I re-generated all the required files in SDK, as mentioned in the embedded-design-tutorial files, so from that, the correct xparameters would have been generated. I just double checked, and for the xilinx tutorial, the gpio leds is at 0x41200000 and for the gpio buttons it is at 0x41240000. That is well within the 0x40000000 to 0x7fffffff memory address ranges for fpga0 devices in the translation table.

 

As for the contents of the xmd_top.tcl file, I got it from the xapp792 design files. This has a the tcl script doing exactly the same thing, i.e. programming the bitstream, connecting to the processor, issuing the rst command, downloading the fsbl, and then downloading the software application.

 

So, I'm using exactly the same setup described in the Xilinx xapp792 to download the program to the ZC702 using Platform Cable USB II, from a command line, and observing the output on another console window. I'm using SDK only to compile and build the binaries. Downloading and debugging bare-metal applications dont' seem to be working with SDK 14.3 on Ubuntu 12.10 64-bit.

 

Elvis Dowson

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Registered: ‎12-30-2008

Re: ZC702: Xil_In32() function hanging for ip cores instantiated on the PL side

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Hi Norman,

                     FYI, I re-ran my original axi_gpio example, and locked the ip instance at address 0x40000000, and same results. The Xil_In32() function hangs.

 

Elvis Dowson

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Xilinx Employee
Xilinx Employee
12,111 Views
Registered: ‎02-01-2008

Re: ZC702: Xil_In32() function hanging for ip cores instantiated on the PL side

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I just looked at the tcl file and it is a different way to initialize the PS.

 

I hope you created the fsbl, otherwise you may have different settings in your design vs the fsbl.

 

You don't mention what your top level is. Whether it's XPS or planahead, you need to export your design to sdk. This action creates ps7_init.tcl and ps7_init.c files in the exported directory. The ps7_init.c is used whenever you create a fsbl. I suggest you use the ps7_init.tcl instead of the method of starting and stoping fsbl.

 

So change xmd_top.tcl to:

#################################

set myvar "Setting FSBL"

#Download Bitstream (make sure board is in JTAG mode)
fpga -debugdevice devicenr 2 -f system_stub.bit

#Connect To Processor
connect arm hw

#Reset The PS and Fabric
rst

#Initialize the PS
source ps7_init.tcl

ps7_init

puts "$myvar"

#Download Software Application
dow axi_vdma_display.elf
 
run

#Disconnect from XMD
disconnect 64

#################################

 

Or, comment out the last two executable lines 'run' and 'disconnect'. Then, at the xmd command prompt, enter the command 'mrd 0x41200000' to read the gpio data register.

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Registered: ‎12-30-2008

Re: ZC702: Xil_In32() function hanging for ip cores instantiated on the PL side

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Hi,

      My top level is created in PlanAhead. I used XPS to specify the system, exit and return to PlanAhead, and then export the hardware and generated bitstream to the SDK. So, the ps7_init.tcl and ps7_init.c files are all created during the export.

 

Elvis Dowson

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Registered: ‎12-30-2008

Re: ZC702: Xil_In32() function hanging for ip cores instantiated on the PL side

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Hi,

     I did as you asked, modified the xmd_top.tcl, and executed an mrd 0x41200000 0xa, after downloading the elf binary to the ZC702 target and get the following error message.

 

ERROR: Cannot Read from target

 

I even deleted my entire system.xmp project from PlanAhead, recreated a new system.xmp, and use the BSB wizard and left the GPIO_SW, and removed the LED_4BIT. So it is the default settings, and probably the simplest GPIO configuration. I mapped the GPIO SW to SW5 on the ZC702, within PlanAhead's system.ucf file.

 

The bitstream generated successfully with 3 warning messages (the PS7 IOBUF, etc, which is normal and can be ignored).

 

I then exported the hardware and bitstream to the SDK, and it still hangs when you try to read the GPIO from it's base address on the PL side.

 

Is there anything else I should look into? This is really weird, it should work with all the default settings but somehow isn't.

 

Elvis Dowson

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Registered: ‎12-30-2008

Re: ZC702: Xil_In32() function hanging for ip cores instantiated on the PL side

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Hi,

      I made some progress. I decided to create a BOOT.bin bootable image and run it from the sdcard, and it worked.

 

ZC702 - GPIO and Timer Test Application
Success: Initialized GPIO, status code = 0
Attempting to set GPIO SW5 data direction
Finished setting GPIO SW5 data direction
Attempting to read GPIO SW5
Finished reading GPIO SW5
Xil_In32: GPIO SW5 register at address 41200000, value = 0

 

In my bootimage, I included the zynq_fsbl, system.bit and the axi_gpio_timer_test_application.elf:

 

the_ROM_image:
{
	[bootloader]/project/xilinx-zc702-timer-gpio-chipscope/sw/zynq_fsbl/Debug/zynq_fsbl.elf
	/project/xilinx-zc702-timer-gpio-chipscope/sw/system_hw_platform/system.bit
	/project/xilinx-zc702-timer-gpio-chipscope/sw/axi_gpio_timer_test_application/Debug/axi_gpio_timer_test_application.elf
}

 

This means that the bitstream and the project is built correctly. However, it is the part relating to downloading the bitstream manually to the target board via XMD that is causing things to fail.

 

How should I do this using XMD? It is a bit unweildy to create a bootable image and copy it each time to the sdcard.

 

Elvis Dowson

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Re: ZC702: Xil_In32() function hanging for ip cores instantiated on the PL side

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Oh, I keep forgeting that part. The level shifters between the PL and PS need to be turned on. In the early versions of tools they were turned on automatically with ps7_init.

 

Now, after you run ps7_init, run the command 'init_user'.

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Registered: ‎12-30-2008

Re: ZC702: Xil_In32() function hanging for ip cores instantiated on the PL side

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Hi,

       Thank you very much for your help!

 

Running the init_user command worked, it enabled the level shifters and I was able to execute the program via XMD and the Platform Cable USB II JTAG probe.

 

BTW, where is init_user defined? I couldn't find it when I searched my eclipse workspace.

 

Here is the xmd_top.tcl file:

 

set fsbl_message "Setting FSBL"
set app_message  "Downloading application"

#Download Bitstream (make sure board is in JTAG mode)
fpga -debugdevice devicenr 2 -f system.bit

#Connect To Processor
connect arm hw

#Reset The PS and Fabric
rst

#Initialize the PS
puts "$fsbl_message"
source ps7_init.tcl
ps7_init
init_user

#Download Software Application
puts "$app_message"
dow axi_gpio_timer_test_application.elf

#Run the application
run

#Disconnect from XMD
disconnect 64

 

Here is the output  from the console running on the host:

 

$ xmd -tcl xmd_top.tcl
Xilinx Microprocessor Debugger (XMD) Engine
Xilinx EDK 14.3 Build EDK_P.40xd
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.
Executing user script : xmd_top.tcl
Programming Bitstream -- system.bit
Fpga Programming Progress ............10.........20.........30.........40.........50.........60.........70.........80.........90........Done
Successfully downloaded bit file.

JTAG chain configuration
--------------------------------------------------
Device   ID Code        IR Length    Part Name
 1       4ba00477           4        Cortex-A9
 2       03727093           6        XC7Z020


JTAG chain configuration
--------------------------------------------------
Device   ID Code        IR Length    Part Name
 1       4ba00477           4        Cortex-A9
 2       03727093           6        XC7Z020

CortexA9 Processor Configuration
-------------------------------------
Version.............................0x00000003
User ID.............................0x00000000
No of PC Breakpoints................6
No of Addr/Data Watchpoints.........1

Connected to "arm" target. id = 64
Starting GDB server for "arm" target (id = 64) at TCP port no 1234
Processor stopped

Target reset successfully

Processor stopped

System reset successfully
Setting FSBL
Info:  Enabling level shifters and clearing fabric port resets
Downloading application
Downloading Program -- axi_gpio_timer_test_application.elf
	section, .text: 0x00100000-0x00102727
	section, .init: 0x00102728-0x0010273f
	section, .fini: 0x00102740-0x00102757
	section, .rodata: 0x00102758-0x00102a67
	section, .data: 0x00102a68-0x00103c5b
	section, .eh_frame: 0x00103c5c-0x00103c5f
	section, .bss: 0x00103c60-0x00103ccb
	section, .mmu_tbl: 0x00103ccc-0x0010bfff
	section, .init_array: 0x0010c000-0x0010c007
	section, .fini_array: 0x0010c008-0x0010c00b
	section, .heap: 0x0010c00c-0x0010e00f
	section, .stack: 0x0010e010-0x00112c0f
Setting PC with Program Start Address 0x00100000
Processor started. Type "stop" to stop processor

RUNNING> Disconnected from Target 64

Disconnected from Target 352

 

And here is the output from the ZC702 terminal:

 

ZC702 - GPIO and Timer Test Application
Success: Initialized GPIO, status code = 0
Attempting to set GPIO SW5 data direction
Finished setting GPIO SW5 data direction                                        
SW5 push button pressed                                                         
Press 0 to exit the application, any other key to continue                      
Attempting to read GPIO SW5 base address                                        
Finished reading GPIO SW5 base address                                          
Xil_In32: GPIO SW5 register at address 41200000, value = 0

 

Elvis Dowson

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Registered: ‎02-01-2008

Re: ZC702: Xil_In32() function hanging for ip cores instantiated on the PL side

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It's in a tcl file that SDK automatically includes.

 

<ise_install>/EDK/data/xmd/zynqutils.tcl

 

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Registered: ‎09-02-2010

Re: ZC702: Xil_In32() function hanging for ip cores instantiated on the PL side

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Hello,

 

this thread really helped me as I was having the exact same problem... I tried to use vivado but had some trouble so went back to PlanAhead14.4 and I guess that is why I had the problem.

However, I don't really understand how come we don't have the same problem when booting through the fsbl.. As far as I know the fsbl does pretty much the same that we do with the tcl scripts.. I mean, I generated a fsbl just to check and I can see the ps7_init(); call no problem, however, I have been trying to locate some call to init_user or similar but could find anything.

So where does the FSBL turn on the level shifters? I am just trying to make sure I understand what is going on.

 

Thanks!!

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Re: ZC702: Xil_In32() function hanging for ip cores instantiated on the PL side

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It will depend on what version of EDK that you compiled FSBL with.

 

In the FSBL source, search for EnablePLtoPSLevelShifter(), FabricInit() and NON_PS_INSTANTIATED_BITSTREAM

 


The NON_PS_INSTANTIATED_BITSTREAM define is available in the case that FSBL is loading a bit file to the PL that doesn't instantiate the PS7. If there is no PS7, you do not want to enable the PL to PS level shifters. Otherwise, the A9s will think that they are receiving an interrupt forever.

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Re: ZC702: Xil_In32() function hanging for ip cores instantiated on the PL side

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Ahaaaa.... I see, EnablePLtoPSLevelShifter() is called by the function which performs the dma transfer to configure the PL, I guess all we would have to do is have our standalone application call this function besides the ps7_init(). Wouldn't it be good to include a commented call to such in init_platform() just like it is done with ps7_init()? just a suggestion.

 

Thanks ;)

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