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Visitor zyee03
Visitor
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Registered: ‎07-05-2018

ZCU102 CDMA does not work, partial data moved from PL to DDR, something wrong I set ?

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I am porting a CDMA design from ZYNQ to ZCU102 platform, it works OK on ZYNQ, but does not work on ZCU102.

Its' a simple CDMA design, just move data from BRAM to PS DDR, tested by devmem tool provided by Xilinx, I feed BRAM the counter data, 0,1,2,3,4,....0xfb,0xfc,0xfd,0xfe,0xff, after DMA transfer, data read from PS linux are wrong, shown as,

0003 9a696aa6 9a9569a6 9a696aa6 0007 9a696aa6 9a9569a6 9a696aa6
000f 9a696aa6 9a9569a6 9a696aa6 000f 9a696aa6 9a9569a6 9a696aa6
001f 9a696aa6 9a9569a6 9a696aa6 0017 9a696aa6 9a9569a6 9a696aa6
001f 9a696aa6 9a9569a6 9a696aa6 001f 9a696aa6 9a9569a6 9a696aa6
003f 9a696aa6 9a9569a6 9a696aa6 0027 9a696aa6 9a9569a6 9a696aa6
002f 9a696aa6 9a9569a6 9a696aa6 002f 9a696aa6 9a9569a6 9a696aa6

looks like only partial data (03, 07, 0f,.. ) moved OK by CDMA.

 

Something wrong I set?  appreciate any guide and suggestion.

 

Vivado, 2017.4.

CDMA/S_AXI_HP0/BRAM, data/addr width, 32bit.

AXI clock, 100MHz.

ZCU102 linux, 64bit, xilinx-zcu102-2017_4.

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Visitor zyee03
Visitor
536 Views
Registered: ‎07-05-2018

Re: ZCU102 CDMA does not work, partial data moved from PL to DDR, something wrong I set ?

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Confirmed this issue was caused by wrong DataWidth set between S_AXI_HP0 and CDMA, irrelvant to linux caches, devmem/mmap still works.

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6 Replies
Adventurer
Adventurer
535 Views
Registered: ‎05-23-2018

Re: ZCU102 CDMA does not work, partial data moved from PL to DDR, something wrong I set ?

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Have you invalidated the CPU caches properly?

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Visitor zyee03
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Registered: ‎07-05-2018

Re: ZCU102 CDMA does not work, partial data moved from PL to DDR, something wrong I set ?

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My app runs in linux, is there a simle way(API) to invalidate CPU cache in linux?
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Adventurer
Adventurer
514 Views
Registered: ‎05-23-2018

Re: ZCU102 CDMA does not work, partial data moved from PL to DDR, something wrong I set ?

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I just looked at your code and saw that you're doing that directly from userspace. I wouldn't recommend to do that, because all proper synchronisation primitives are available inside the kernel. There are drivers available for most (all?) dma-engines from xilinx. Try using them, or at least use them as a reference.

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Visitor zyee03
Visitor
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Registered: ‎07-05-2018

Re: ZCU102 CDMA does not work, partial data moved from PL to DDR, something wrong I set ?

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Thank for driver suggestion, klasha,
but simple devmap/mmap app way working/acceptable on most soc linux-es as I knew, include zynq, driver is bit hard to understand/maintain.

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Visitor zyee03
Visitor
537 Views
Registered: ‎07-05-2018

Re: ZCU102 CDMA does not work, partial data moved from PL to DDR, something wrong I set ?

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Confirmed this issue was caused by wrong DataWidth set between S_AXI_HP0 and CDMA, irrelvant to linux caches, devmem/mmap still works.

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Visitor long.k
Visitor
46 Views
Registered: ‎06-19-2018

Re: ZCU102 CDMA does not work, partial data moved from PL to DDR, something wrong I set ?

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Hi,

I designed the full system as you posted. However, I met the following errors. 2.PNG

The problem is I can not modify the ID-WIDTH of either /zynq_ultra_ps_e_0/S_AXI_HP0_FPD or /axi_interconnect_1/xbar/M00_AXI. 

How can I  resolve the problems? (I am using Vivado 2018.1)

 

Thanks!

 

 

 

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