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Visitor bgiesing
Visitor
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Registered: ‎05-09-2017

Zynq-7000 Pull-up/down Resistor Value Thread

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We are using Zynq-7030 and are confused by the pre-configuration weak pull-up specificaitons, the MIO boot strap mode pull requirements, and the actual pull-ups/downs placed in the PL IOB configurations.

Multiple threads have addressed the "what is the internal resistor value" question for the pre-configuration pull-ups and the PS MIO by referring to the IRPU and IRPD specifications in the datasheet.  If we look at these currents, we find the following:

IRPU (Vcco=3.3V): 90-330uA --> 36.7k-10k

IRPD (Vcco=3.3V): 68-330uA --> 48.5k-10k

IRPU (Vcco=1.8V): 34-220uA --> 52.9k-8.2k

IRPD (Vcco=1.8V): 45-180uA --> 40k-10k

Given the specifications above, the suggested values of 20k for the MIO seem to be inadequate to assure a valid logic level.  Even the Xilinx generally accepted value of 4.7k seems inadequate in the worst cases.

For pre-configuration PL pins, we have peripherals that we want to guarantee logic levels for on certain control pins and need to understand how strong the pull should be to overcome the internal pre-configuration pulls.

Is it possible that the pre-configuraiton and MIO pulls are actually weaker than the pad pulls enabled in the PL IOB, for which the IRPU/IRPD seem to be specifically targeted?

Thank you,

Brian

PS - same pre-configuration weak pull-up value question holds for an Ultrascale Kintex we are using.

 

 

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Highlighted
141 Views
Registered: ‎01-08-2012

Re: Zynq-7000 Pull-up/down Resistor Value Thread

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UG585 Appendix B gives the default states of the MIO control registers.  These have the default state for the PULLUP bit set to 1 (enabled) for MIO bits 0-1, 9-53 and 0 (disabled) for MIO bits 2-8.  MIO bits 2-8 are the boot mode select bits.

These are the default states for those control registers after reset.  The FSBL (or later software such as your operating system) may change these values, but they are guaranteed to have the pullup disabled just after the release of reset, which is when the internal boot ROM samples the levels on MIO bits 2-8 to determine the boot mode.

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Scholar drjohnsmith
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Registered: ‎07-09-2009

Re: Zynq-7000 Pull-up/down Resistor Value Thread

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The pull up / down 'resistors' on the chip are current mirrors, not real resistors.
They are not intended to pull up as you are thinking of them, they are designed for floating lines, a hang over form the old tri state bus days.
If you need pull up / down, then you need to do that on your board. 0201 , or 01005 resistors take up very little room,
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Visitor bgiesing
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Registered: ‎05-09-2017

Re: Zynq-7000 Pull-up/down Resistor Value Thread

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Right... but it's the value that is the question.  Other threads responded with use a value that is sufficient to overcome the IRPU/IRPD current specifications, but then Xilinx itself uses 20k's, which are not sufficient based on those specifications.

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Registered: ‎01-08-2012

Re: Zynq-7000 Pull-up/down Resistor Value Thread

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Pullup or pulldowns are not enabled on the MIO pins used for boot selection.  Xilinx guarantees that 20k ohm will work for boot selection (assuming there's no great amount of PCB leakage).  I believe them and you should too.  In addition, there are plenty of designs in the field using 20k pullup or pulldown resistors for boot selection that work fine over PVT.

For regular PL SelectIO with pull up/down enabled, you will need something much stronger than 20k, as you noted.

Also pay attention to what @drjohnsmith said regarding the use of FETs rather than resistors.  This means, for a worst case design, you should model the pull up/down current as a current source rather than a resistor.  This means your external resistor may need to have a slightly lower resistance than the value you would calculate if the pull up/down inside the FPGA was just a resistor.

For my designs, I try really hard to design my external circuit so that the levels on the pins are chosen so I never have to fight the internal pull up/down with an external resistor.

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Visitor bgiesing
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Registered: ‎05-09-2017

Re: Zynq-7000 Pull-up/down Resistor Value Thread

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"Pullup or pulldowns are not enabled on the MIO pins used for boot selection."  Are you saying they are not enabled prior to boot and config, or not enabled period?  Is there a piece of documentation that states this?

For example, Table 6-9 of UG585 indicates that the boot mode pins themselves can certainly have an internal pull-up enabled - but it doesn't define when exactly that pull-up becomes present.

"I believe them and you should too."  Sure... trust, but verify.

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Highlighted
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Registered: ‎01-08-2012

Re: Zynq-7000 Pull-up/down Resistor Value Thread

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UG585 Appendix B gives the default states of the MIO control registers.  These have the default state for the PULLUP bit set to 1 (enabled) for MIO bits 0-1, 9-53 and 0 (disabled) for MIO bits 2-8.  MIO bits 2-8 are the boot mode select bits.

These are the default states for those control registers after reset.  The FSBL (or later software such as your operating system) may change these values, but they are guaranteed to have the pullup disabled just after the release of reset, which is when the internal boot ROM samples the levels on MIO bits 2-8 to determine the boot mode.

Visitor bgiesing
Visitor
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Registered: ‎05-09-2017

Re: Zynq-7000 Pull-up/down Resistor Value Thread

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The needle in the proverbial haystack! Thank you!

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130 Views
Registered: ‎01-08-2012

Re: Zynq-7000 Pull-up/down Resistor Value Thread

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All the information needed was in UG585, but at about 1.8k pages long, I appreciate that it's easy to miss what you are looking for.

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