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Adventurer
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Registered: ‎08-23-2012

Zynq: MDIO to "GMII to RGMII" LogiCORE in PL not working / Vivado 2014.1

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Vivado 2014.1

 

I do use ENET1 on Zynq routed through PL via GMII2RGMII.

External PHY is Marvell 88E1510. PHYAddr= 0 (ok, not nice, but working)

Bitrate is fixed 100 Mbit/s.

 

GMII2RGMII is configured

- external clock (25 MHz)

- Shared Logic in core

- PHYAddr= 8 (default)

 

This works fine:

- SW from xapp1026 / iperf on PC (TCP-connection nearly 10 MBytes/s == Max for 100Mbit)

- MDIO communication from ENET1 through GMII2RGMII to PHY

 

Whats wrong:

- When reading any of the 32 register of the GMII2RGMII the result is alway 0x0.

 

--------------------------------------------------------------------------------

console:

 

PhyAddr #0: 0x3100, 0x7969, 0x141, 0xDD1, 0x180, 0x45E1, 0x7, 0x2801, 0x0, 0x0, 0x4000, 0x0, 0x0, 0x3, 0x0, 0x3000, 0x3060, 0x7C08, 0x0, 0x1F40, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x40, 0x0, 0x0, 0x0
, 0x0, 0x0,
PhyAddr #1: 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
PhyAddr #2: 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
PhyAddr #3: 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
PhyAddr #4: 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
PhyAddr #5: 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
PhyAddr #6: 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
PhyAddr #7: 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
PhyAddr #8: 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
--------------------------------------------------------------------------------

 code:

 

    for (PhyAddr = 0; PhyAddr <= 8; PhyAddr++)

    {
        xil_printf("PhyAddr #%d: ",PhyAddr);
        for(RegAddr= 0; RegAddr <= 31; RegAddr++)
        {
            Status = XEmacPs_PhyRead(EmacPsInstancePtr, PhyAddr, RegAddr, &PhyReg);
            xil_printf("0x%x, ",PhyReg);
        }
        xil_printf("\r\n");
    }

--------------------------------------------------------------------------------

 

 

 

 

 

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Adventurer
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Registered: ‎08-23-2012

Re: Zynq: MDIO to "GMII to RGMII" LogiCORE in PL not working / Vivado 2014.1

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6 Replies
Adventurer
Adventurer
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Registered: ‎08-23-2012

Re: Zynq: MDIO to "GMII to RGMII" LogiCORE in PL not working / Vivado 2014.1

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same problem with Vivado 2014.2.

 

 

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Visitor ashiar01
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Registered: ‎08-04-2014

Re: Zynq: MDIO to "GMII to RGMII" LogiCORE in PL not working / Vivado 2014.1

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We are having issues with this core as well. I think there is a possible bug in this core. The document for this core says the rx_reset is active low, but if you bring this into the block design flow, the tool chokes if you connect an active low reset to this pin. The unencrypted portion of the core shows that the tx_reset and the rx_reset are or'ed which doesn't make any sense as the tx_reset is listed as active high in the design doc.

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Adventurer
Adventurer
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Registered: ‎08-23-2012

Re: Zynq: MDIO to "GMII to RGMII" LogiCORE in PL not working / Vivado 2014.1

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4,251 Views
Registered: ‎04-28-2015

Re: Zynq: MDIO to "GMII to RGMII" LogiCORE in PL not working / Vivado 2014.1

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Hi:

 

What was your solution. I  think I have the same problem?

 

Regards

Tony

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Adventurer
Adventurer
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Registered: ‎08-23-2012

Re: Zynq: MDIO to "GMII to RGMII" LogiCORE in PL not working / Vivado 2014.1

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problem: MDIO to GMII2RGMII is not working properly -> GMII2RGMIII can not be configured

 

workaround: use fixed configuration. connect the right clock to the GMII2RGMII. Configure BSP to this fixed transfer rate (10/100/1000 Mbit/s). -> (25 MHz == 100 Mbit/s for me) this is working for my use case.

 

Since there was no feedback from Xilinx employees, I think there is a bug inside GMII2RGMII-IP.

 

I have not tried this with later Vivado releases.

 

Which version of Vivado are you using?

 

 

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Re: Zynq: MDIO to "GMII to RGMII" LogiCORE in PL not working / Vivado 2014.1

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