UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Explorer
Explorer
2,199 Views
Registered: ‎09-03-2013

Zynq : MIO pin mapping, pin 12 problem

Hello,

 

We are using Vivado 2013.4 with xc7z030ffg676-2 chip.

 

We use parallel NOR flash via MIO interface. According to TRM UG585 table 2-4 there is “hole” in NOR flash MIO mapping in pins 12 and 14. However we cannot use MIO pin 12 as GPIO pin in processing system peripheral I/P pins MIO/EMIO selection.  Either we cannot select it or we have conflict with parallel NOR flash when e.g. selecting Ethernet reset to MIO pin 12. In Vivado there seems to be some "wait" input for parallel NOR flash Zynq connection in pin MIO(12).....

 

Regards,

Ville-Veikko

0 Kudos
1 Reply
Explorer
Explorer
2,169 Views
Registered: ‎09-03-2013

Re: Zynq : MIO pin mapping, pin 12 problem

Hi,

 

I got answer from Xilinx expert. TRM UG585 is correct, MIO pin 12 should be used as GPIO  when parallel NOR flash is used.  This is issue with the Vivado tool.

 

Regards,

Ville-Veikko

0 Kudos