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Registered: ‎12-06-2013

Zynq: What is the pull-up resistor value of the MIO

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Was unable to find this in the datasheet or elsewhere.

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Explorer
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Registered: ‎12-06-2013

Re: Zynq: What is the pull-up resistor value of the MIO

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@glena

 

The final word from Xilinx:

I believe the Irpu & Irpd shown in table 3 of DS187 applies to the MIO in addition to the PL selectIO.
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Registered: ‎01-08-2012

Re: Zynq: What is the pull-up resistor value of the MIO

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Zynq Datasheet DS187

 

The parameter IRPU gives the pullup current.

 

Please note the following:

 

  1. The tolerance on IRPU is really bad (as much as 10:1 in some cases), so don't use this for any circuit that requires an accurate pullup current.
  2. The pullup current varies with supply voltage and temperature.
  3. They don't actually say that a resistor is used.  It's likely to be a P-channel FET.  This has a V-I characteristic more like a current source than a resistor, which actually makes it a better pullup.  That said, Xilinx only specify one point on the curve (the current when the pin voltage is 0V).

 

Actually they do say that resistors are used.  See Footnote 2 to Table 5 in DS187, for example.  I'm going to assume that's a mistake though :)

 

Regards,

Allan

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Registered: ‎12-06-2013

Re: Zynq: What is the pull-up resistor value of the MIO

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@allanherriman

 

In the TRM it is always referred to as a pull-up also. However, the Irpu that you mentioned is under the PL category so they don't actually define anything specific to Irpu for the PS. As for the "resistor value" Xilinx has always had an excessive amount of slop indicating it is most likely a FET as you noted.

 

The problem driving this question relates to how hard I need to pull down the MIO when using the SWDT. Since the SWDT is oddly an active high signal (and SRST_N is active low) I need to guarantee that this pin is pulled low after Zynq initialization to avoid a reset lock-up. All of the MIO pins that are configurable with the SWDT have the pull-up setting by default in the SCLR registers (I am out of PL pins).....that is a problem. Also, I need my entire design to go into a proper reset (including the PL) when the SWDT asserts, not just the processor(s).

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Registered: ‎01-08-2012

Re: Zynq: What is the pull-up resistor value of the MIO

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Hi Jeff,

 

It was an assumption on my part that the same pullup design would be used for both the PL and PS MIO.  As you noted, this is not supported by the documentation.  Perhaps someone from Xilinx would like to comment?

 

 

I had a similar design issue on an old Zynq board of mine.  I had a GPIO signal mapped to an MIO pin.  It was active high, and the downstream device had a threshold of 0.4V.  A false high had bad consequences.  I used a rather strong pulldown, 120 ohm from memory, but that may have been overkill.

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Registered: ‎12-06-2013

Re: Zynq: What is the pull-up resistor value of the MIO

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@allanherriman

 

You had the problem that I am worried about. 120 ohm?!

 

I'll push this to a webcase and update. Thanks for letting me know.

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Registered: ‎12-06-2013

Re: Zynq: What is the pull-up resistor value of the MIO

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@glena

 

The final word from Xilinx:

I believe the Irpu & Irpd shown in table 3 of DS187 applies to the MIO in addition to the PL selectIO.
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