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Contributor
Contributor
340 Views
Registered: ‎04-06-2018

ila showing incomplete AXI Stream transfer over DMA

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Hi ,  I want to debug my custom AXI Stream protocol for DMA transfer. Then I created a smaller setup for standalone with a loop back at the DMA and using simple transfer pooling. The transfer happens right via SDK xaxidma_example_simple_poll.c from /SDK/2018.2/data/embeddedsw/XilinxProcessorIPLib/drivers/axidma_v9_7/examplesbut when I probe using ILA I see only 4 TDATA from a package of 16 and the the TDATA has wrong numbers , since I am transferring a gradient from 0 to 15. I am wondering if my ILA settings are right , which settings should I check though ? freq ? triggering ? It is set to trigger from TVALID = 1 .

-- Entering main() ---

Data ok 0: 0/0

Data ok 1: 1/1

Data ok 2: 2/2

Data ok 3: 3/3

Data ok 4: 4/4

Data ok 5: 5/5

Data ok 6: 6/6

Data ok 7: 7/7

Data ok 8: 8/8

Data ok 9: 9/9

Data ok 10: A/A

Data ok 11: B/B

Data ok 12: C/C

Data ok 13: D/D

Data ok 14: E/E

Data ok 15: F/F

Successfully ran XAxiDma_SimplePoll Example

--- Exiting main() ---

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Screenshot from 2018-11-25 11-26-16.png
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Xilinx Employee
Xilinx Employee
300 Views
Registered: ‎02-01-2008

Re: ila showing incomplete AXI Stream transfer over DMA

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Looks like you are triggering on the correct stuff. Usually I trigger on TVALID AND TREADY but your capture shows both are active.

The incorrect data could be due to not flushing cache after writing your expected data to DDR before starting DMA.

To get a bigger picture, I usually use System ILA, enable 4 interfaces, change two of the interfaces to "axis rtl" and then do a capture so that you see what AXI4 accesses are doing at the same time as the AXIStream interfaces. Hint: in 'Interface Type" start typing 'axis' to find the correct interface type. The only difference between System ILA and ILA is that the system ILA recognizes the axi buses (and many other bus types).

Now you should be able to see the axi4 interfaces also.

pic.png

 

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Xilinx Employee
Xilinx Employee
301 Views
Registered: ‎02-01-2008

Re: ila showing incomplete AXI Stream transfer over DMA

Jump to solution

Looks like you are triggering on the correct stuff. Usually I trigger on TVALID AND TREADY but your capture shows both are active.

The incorrect data could be due to not flushing cache after writing your expected data to DDR before starting DMA.

To get a bigger picture, I usually use System ILA, enable 4 interfaces, change two of the interfaces to "axis rtl" and then do a capture so that you see what AXI4 accesses are doing at the same time as the AXIStream interfaces. Hint: in 'Interface Type" start typing 'axis' to find the correct interface type. The only difference between System ILA and ILA is that the system ILA recognizes the axi buses (and many other bus types).

Now you should be able to see the axi4 interfaces also.

pic.png

 

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Contributor
Contributor
279 Views
Registered: ‎04-06-2018

Re: ila showing incomplete AXI Stream transfer over DMA

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tks john !

it was super nice and easy , and looks like the example squeezes 4 bytes of my packet into the 32 bits of the data bus, that's y I transmit 32 words , but only shows 8 words in the wave , inside each word is my original data !

I will try to figure out to transmit each word of 32 bits.

BR

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Screenshot from 2018-11-27 18-03-54.png
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