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Registered: ‎05-14-2017

100G Ethernet LBUS/AXI bus format

When using the 100G Ethernet IP (PG203 v3.0), it doesn't describe the 512-bit LBUS/AXI interface format or data structure.

In order to process this interface, I believe the user need this information.

From the IEEE 802.3-2012 Ethernet frame, does the IP remove the SFD, DA, SA and FCS and only display the Ethernet Payload (MAC Client Data) of does it display the complete Ethernet Frame on this interface?

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2 Replies
Xilinx Employee
Xilinx Employee
Registered: ‎05-01-2013

回复: 100G Ethernet LBUS/AXI bus format

From DA, SA...

FCS is optional

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Observer aforencich
Registered: ‎08-14-2013

Re: 100G Ethernet LBUS/AXI bus format

The core removes the preamble/SFD, but makes it available on a separate signal and has a separate signal to optionally insert a custom preamble.  The addresses and length/type field are always passed through.  The FCS is optionally checked and stripped or passed through (for receive) and generated and inserted or passed through (on transmit).  The default configuration is to handle as much as possible internally (preamble and FCS) and pass through the rest of the frame (addresses, eth type, and payload).  Note that unlike many other MACs, you must zero-pad transmit frames out to at least 64 bytes yourself, otherwise strange things happen.  And yes, I got bit by this one myself, took a while to figure out what the issue was (why can I run UDP netperf (after stuffing ARP tables), but ARP and ping don't work???). 

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