09-21-2018 03:36 AM
I'm designing a board containing two Zynq Ultrascale+ FPGAs. A 100G chip-to-chip connection exists between the two FPGAs.
I would like to perform Signal Integrity analysis on this interface. Is there any document specifying what can be the signal losses and what an ideal eye-diagram should look like at the receiver for error-free decoding?
09-21-2018 04:48 AM
100 GbE, I assume. Because they use the MGT, you can start with UG476, chapter 5 (Board Design Guidelines)
An ideal eye diagram is what anyone has never seen... what you need is the eye mask. I would look into the IEEE Std 802.3ab that is the 40/100 G Ethernet.
09-21-2018 08:05 AM
In normal use, at 100G, I think you do not get error free, the use of the FEC is all but mandatory
If this is fpga to fpga, are you going via connectors or just tracked ?
its fun stuff to try to monitor with a scope !
09-21-2018 09:11 AM
Thank you for your replies.
@johnvivm, Yes, it is 100 Gb ethernet. In my case, it is UG583 and UG587 for Ultrascale+ devices. I am indeed looking for the eye mask and I was going to look into the IEEE spec. I was hoping that some Xilinx doc might have some of the relevant parts from the IEEE doc.