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Adventurer
Adventurer
406 Views
Registered: ‎08-04-2016

100G board design specifications

Hello,

 

I'm designing a board containing two Zynq Ultrascale+ FPGAs. A 100G chip-to-chip connection exists between the two FPGAs.

I would like to perform Signal Integrity analysis on this interface. Is there any document specifying what can be the signal losses and what an ideal eye-diagram should look like at the receiver for error-free decoding?

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3 Replies
Voyager
Voyager
394 Views
Registered: ‎08-16-2018

Re: 100G board design specifications

100 GbE, I assume. Because they use the MGT, you can start with UG476, chapter 5 (Board Design Guidelines)

An ideal eye diagram is what anyone has never seen... what you need is the eye mask. I would look into the IEEE Std 802.3ab that is the 40/100 G Ethernet.

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Scholar drjohnsmith
Scholar
374 Views
Registered: ‎07-09-2009

Re: 100G board design specifications

In normal use, at 100G, I think you do not get error free, the use of the FEC is all but mandatory

 

If this is fpga to fpga, are you going via connectors or just tracked ?

 

its fun stuff to try to monitor with a scope !

 

 

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Adventurer
Adventurer
365 Views
Registered: ‎08-04-2016

Re: 100G board design specifications

Thank you for your replies.

 

@johnvivm, Yes, it is 100 Gb ethernet. In my case, it is UG583 and UG587 for Ultrascale+ devices. I am indeed looking for the eye mask and I was going to look into the IEEE spec. I was hoping that some Xilinx doc might have some of the relevant parts from the IEEE doc.

 

@drjohnsmith

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