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Registered: ‎07-27-2018

100G rx_alignment on Post Synthesis functional simulation


I'm trying to simulate a US+ 2019.1 100G xilinx IP, I have a custom design:

1) board kcu116

2) clock for init_clk 125Mz

3) CAUI-4 with 161.1328 MHz for gt clk

4) AXI stream and AXi4-Lite to control rx_alignment from CMAC internal register

5) testbench in which I connect gt_rx/tx port in loopback

In Behavioural simulation I have no problem and I can see alignment and the packet trasmitted form AXI Stream Tx port that arrives to Rx of CMAC.

Instead If I run simulation after Post Synthesis, both Functional and Timing simulation I don't get the alignment, I tried for 1ms of simulation.

The same happens with an example design project of CMAC provide by Xilinx, the behavioural works but after synthesis it doesn't get the alignment.

Have I to wait more time in the simulation?

Is there a start-up timing to wait after the boats is powered on?

I release reset in this sequence:

1) release reset for cmac sys:reset

2) release reset for both gt:rx and gt_tx path at the same time

3) then I release reset of control logic

the control logic wait to poll the cmac on axi4-lite port for about 30us the starts.

I don't know if the 2 thinks are related, however the design havven't any timing issue on timing summary.

Thank you!

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4 Replies
Xilinx Employee
Xilinx Employee
Registered: ‎05-01-2013

回复: 100G rx_alignment on Post Synthesis functional simulation

Have you set "-d SIM_SPEED_UP"?

Do you enable RSFEC?

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Registered: ‎04-01-2018

Re: 100G rx_alignment on Post Synthesis functional simulation

HI @namabo 

As I understood from your description about simulation: Behaviour simulation with SIM_SPEED_UP applied will take less time than the Post synthesis simulation.Hardware testing will take the time equivalent to Post synthesis simulation for the rx_alignment. As I simulated some time back it takes about 1.683ms to get rx_alignment. 


If you beleive the funcitonal simulation takes even more than this time for your custom design we can think of resets.Please share your simualtion screens.

Don't forget to reply, give kudo and accept as solution
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Registered: ‎07-27-2018

Re: 100G rx_alignment on Post Synthesis functional simulation

Hi @kgadde,

I confirm you that example design converges in 1.6 ms to rx_alignment in Post functional simulation.


I'm trying to simulate the post-functional with RS-FEC on the example design It takes a lot of time for now I'm at 2.5ms (about 7h).


I will let you know.

Thank you for your support guys.



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Registered: ‎07-27-2018

Re: 100G rx_alignment on Post Synthesis functional simulation

I finished the simulation on the example design and

after 10ms it doesn't reach the alignment yet, it ends with the following errors:

ERROR : Rx_Aligned failed - Time Out Error
ERROR : Time Out Error

Now, these are the first experiment I do with post synth and post impl simulation, in my design I skept this point because I preferred to go in the real hardware with ILA or System ILA.

I extend the thread and I would like to know your personal approach:

Do you perform all the simulation steps in a project or do you prefer to consider just the behavioural sim or simulation subset? If so which subset do you use?

The simulation time is very high, 3/4hours for post-synthesis, I didn't try the post implementation but I think it could easly reach one day of simulation.

Thank you


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