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g.pavlikh
Participant
Participant
723 Views
Registered: ‎09-10-2012

10G/25G Ethernet Subsystem, LPM mode

I had some issues with bad RX frames in 10G mode with my design on xcku060-ffva1156-1-c, and after some search I found advice to use LPM mode (mentioned in https://forums.xilinx.com/t5/Networking-and-Connectivity/Bad-frames-due-to-FCS-error-in-10G-MAC/td-p/560067 ).
I've updated Vivado to 2019.1 and checked 10G/25G Ethernet Subsystem v3.0 core. It has RX Equalization Mode setting, so at first I generated core with Auto mode, checked it for presence of RX errors, then generated core with LPM mode and checked it. Sadly, RX errors rate became worse. I compared sources for this two cores, and found some odds:

1. According to UG576, "To switch from DFE to LPM mode, set RXLPMEN = 1".
2. This pin is located in \ip_0\synth\gtwizard_ultrascale_v1_7_gthe3_common.v file. Its value depends on two parameters GTHE3_CHANNEL_RXLPMEN_TIE_EN and GTHE3_CHANNEL_RXLPMEN_VAL and one input port GTHE3_CHANNEL_RXLPMEN by this equation:

if (GTHE3_CHANNEL_RXLPMEN_TIE_EN == 1'b1)
assign GTHE3_CHANNEL_RXLPMEN_int = {NUM_CHANNELS{GTHE3_CHANNEL_RXLPMEN_VAL}};
else
assign GTHE3_CHANNEL_RXLPMEN_int = {NUM_CHANNELS{GTHE3_CHANNEL_RXLPMEN}};

3. If we follow GTHE3_CHANNEL_RXLPMEN port, we go through these files:
\ip_0\synth\corename_gt_gthe3_channel_wrapper.v
\ip_0\synth\corename_gt_gtwizard_gthe3.v
\ip_0\synth\corename_gt_gtwizard_top.v
\ip_0\synth\corename_gt.v
\corename\corename_wrapper.v

In last file we have this assignment in both cores, Auto and LPM:
assign rxlpmen_in_0 = 1'b0;

4. Parameter GTHE3_CHANNEL_RXLPMEN_VAL is defined in corename_gt_gthe3_channel_wrapper.v file and it is different for Auto and LPM mode - 0 for Auto and 1 for LPM.
5. But parameter GTHE3_CHANNEL_RXLPMEN_TIE_EN is zero in both cores.

As I think, the idea behind RX Equalization Mode was to control it by GTHE3_CHANNEL_RXLPMEN_VAL parameter, but someone forgot to change GTHE3_CHANNEL_RXLPMEN_TIE_EN accordingly.
After manual change of GTHE3_CHANNEL_RXLPMEN_TIE_EN to 1 RX errors was eliminated.

I've also checked 40G/50G Ethernet Subsystem v2.5 core - it has similar error, LPM mode is always disabled.

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guozhenp
Xilinx Employee
Xilinx Employee
683 Views
Registered: ‎05-01-2013

OK.

So after you enabled LPM successfully, the code errores are solved?

It sounds great and is very useful to other engineers.

Do you have any more question?

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g.pavlikh
Participant
Participant
668 Views
Registered: ‎09-10-2012

We are still evaluating 40G core.

10G core is working fine with mentioned changes, but we are using only short cables, something like 5 meters.

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