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Observer kubilaysavci
Registered: ‎12-20-2012

10G Ethernet Subsystem v3.1: txusrclk2_out is not active on KCU105 board (ultrascale device)

I'm developing a firmware with Vivado 2016.4 for the KCU105 board which uses 10G ethernet subsystem v3.1 IP core. For the moment, the design continuously transmits ethernet packets to PC over SFP+ fiber optics with some interval.


The IP core is configured for 10G Base-R 64bit@156.25MHz Axi datastream configuration. Shared logic is included and the input reference clock is provided by the board's programmable clock (SFP GT in bank 226 sourced by Si570 clock in Bank 227, 156.25MHZ).


As stated in PG157 product guide,  txusrclk2_out  must be used for the user logic in Ultrascale devices and I'm using the txusrclk2_out clock for the transmitter user logic which triggers the tx frame axi-stream.


However, the txusrclk2_out clock is not coming out from the ip core (is always low) and I can't drive the transmitter user logic. Hence I neither see any traffic on network nor capture any eth packet on PC.


When I connect the coreclk_out to the user logic, everything works fine,and I can capture transmitted eth packets on PC.


In order to test both clocks, I wrote a simple ~1Hz blinking led process(shown below) in vhdl.  When using txusrclk2_out  the led did'nt blink because txusrclk2_out is not active. However when using coreclk_out the led blinks with roughly 1.7sec interval. I think this proves that I can't get any clock from txusrclk2_out port of the core. 



if (rising_edge (clk)) then

       counter<=counter +1;

end if;

led <=counter(28);


I've also checked the KCU105 10GBASE-R Ethernet TRD User Guide UG921-v2016.4 and in that design, contrary to  what PG157 says,  coreclk_out is used for the user logic.


Now I'm confused! which is wrong? which is correct?  


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