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Adventurer
Adventurer
3,861 Views
Registered: ‎08-26-2013

10G PCS/PMA RX simulation problem

Hi,

Using 10G PCS/PMA core in simulation, displays same good functionality same as hardware real implementation in TX side but RX side of same link including MAC and PCS/PMA core is failed during simulation and implementation. It's important that after adding RX logic(including processing received packet and links between mac & PCS/PMA etc), both TX and RX link are failed exactly and txc and rxc lines show this result too. What's the problem with my design and thanks for any hints...

 

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mhmontazeri61

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Moderator
Moderator
3,791 Views
Registered: ‎02-16-2010

If you are looking to use MAC and PCS/PMA together, can you check 10G Ethernet subsystem IP (or)10G/25G Ethernet subsystem IP?
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Xilinx Employee
Xilinx Employee
3,781 Views
Registered: ‎02-06-2013

Hi

 

What exactly are  you monitoring when you say RX is failing and what is the extra logic you have added when you see both Tx and RX failing.

 

Can you upload the simulation dump high lighting the issue you are seeing.

Regards,

Satish

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Contributor
Contributor
3,757 Views
Registered: ‎09-08-2015

Hi ,

 

Did you monitor you reset signals? are they stable while the cable is connected to the Ethernet port? Is control signals rxc and txc are in IDLE?

Did you connect the coreclk and dclk to a free-running clock?

 

Kind regards,

Pedram Kermani

 

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Adventurer
Adventurer
3,748 Views
Registered: ‎08-26-2013

@venkata,

I'm during implementation of youyr mentioned cores. But my selected device does not support 25G lanes(i think).

 

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mhmontazeri61

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Adventurer
Adventurer
3,740 Views
Registered: ‎08-26-2013

@yenigal,

Below attached PNGs show RX and TX lines of my instantiated core. Results gathered by ila inserted cores. Thanks for more info.

 

Regards

mhmontazeri61

RX.PNG
TX.PNG
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Adventurer
Adventurer
3,733 Views
Registered: ‎08-26-2013

@pd.kermani,

My design in upstream side is exactly successful and your questions are true but seems they're not my problem at this time, though about your questions: all related signals are true and resets are inactive and two clocks are in free running normal state.

 

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mhmontazeri61

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Xilinx Employee
Xilinx Employee
3,699 Views
Registered: ‎02-06-2013

Hi

 

I see remote faults transmitted on the TX which will happen when there is a local fault.

 

Below are the causes which can cause local fault which triggers the remote fault.

 

First check which of this is happening and resolve it.

 

The transceiver has not locked or the receiver is being reset.

• The block lock state machine has not completed.

• The BER monitor state machine indicates a high BER.

• The elastic buffer has over/underflowed

 

Regards,

Satish

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Adventurer
Adventurer
3,682 Views
Registered: ‎08-26-2013

@yenigal,

Thanks for your reply. I'm investigating your mentioned cases and i inform about the result certainly. Some problems exist that i questioned in the other posts and some of they are without any answer yet like the reason of unlock but working my core properly.

 

Regards

mhmontazeri61

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Xilinx Employee
Xilinx Employee
3,642 Views
Registered: ‎05-01-2013

What's the link partner in your test?

If you do GT near end PMA loopback, can the design work?

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Contributor
Contributor
2,290 Views
Registered: ‎11-21-2016

@mhmontazeri61

 

Hi,

 

1. Try connecting a Link Target of same 10G compatibility. 

2. The 10G PCS have to be reset and configured appropriately for proper working.

3. See if you can receive Character '9C' on the receive side of XGMII Interface. 9C means a sequence of data.

4. Set sim_speedup_control to 0 initially and then set it to 1 after PHY's reset is complete.

5. See if core_status goes from 0x00 to 0x01. This shall indicate the PCS block is ready to function.

6. Monitor the resetdone signal of the PCS.

 

Regards,

Suraj

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