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Observer
Observer
3,401 Views
Registered: ‎07-31-2017

10G PCS PMA multiple core instance

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Hi,

 

I want to use more than four PCS/PMA IP core, so my design require more than a single QUAD of transceivers. I follow the 10G Ethernet PCS/PMA v6.0 LogiCORE IP Product Guide  (pg068), wich says in that case I have to generate all the core instances with  Include Shared Logic in example design. The product guide writes: " The shared logic should then be manually edited to create the correct structure of the IBUFDS, GT_COMMON and GT_CHANNEL blocks.". I've got a few problems with the COMMON block. I generate an example design in an other project with an IP core with same settings and Itry to figure out, how can I write a COMMON block. But in the example design this block seems like an other IP core, so it doesn't help it so much. ( Also the BUFFERs of the example design are usefull and I use those in my project.)

 

So my question: How can I make a COMMON block, or more COMMON blocks if it necessary for my 10G PCS PMA multiple core instance project? Or something is wrong with my design flow? Should I generate the IP cores with different options? Or can I generate somehow a COMMON block after the PCS IP Core has been generated?

 

I use Vivado 2017.1 and a Xilinx UltraScale Kintex FPGA.

 

Thanks,

floorbalint

 

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Moderator
Moderator
5,441 Views
Registered: ‎07-30-2007

Re: 10G PCS PMA multiple core instance

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There is only one COMMON block per quad and there is only 1 IBUFDS_GTE* per reference clock input.  Your design has likely instantiated 2 and tried to place them in the same spot. 

 

 




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Xilinx Employee
Xilinx Employee
3,383 Views
Registered: ‎02-06-2013

Re: 10G PCS PMA multiple core instance

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Hi

 

You need only one common block for Quad and the gt common module file can be found in the example design files when shared logic in example design is selected.

Regards,

Satish

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Observer
Observer
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Registered: ‎07-31-2017

Re: 10G PCS PMA multiple core instance

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Hi!

 

Thanx for the reply! I try to implement my design as You said. I create two PCS with Shared logic in example design, and after I copyed the COMMON block's files to the project and I instantiates it and connect the ports as in the example design. I connect all the qpll0 wires as the same as in the example, but the vivado says it can not place the qpll0outclk and qpll0outrefclk signals. 

 

How should I place the common block?

 

Thanks,

floorbalint

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Moderator
Moderator
5,442 Views
Registered: ‎07-30-2007

Re: 10G PCS PMA multiple core instance

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There is only one COMMON block per quad and there is only 1 IBUFDS_GTE* per reference clock input.  Your design has likely instantiated 2 and tried to place them in the same spot. 

 

 




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Observer
Observer
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Registered: ‎07-31-2017

Re: 10G PCS PMA multiple core instance

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Thank You for the replys!  Things getting clearer!

 

Regards,

floorbalint

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Contributor
Contributor
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Registered: ‎10-14-2018

Re: 10G PCS PMA multiple core instance

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So if for example I implement 3 quad, I generate a total of 12 pcs/pma cores , and then I need to create 3 seperate COMMON blocks (one for each quad), and then I share outputs from each common block to 4 pcs/pma cores on the same quad.

 

however, I think I also need the shared clock and reset block also? 

 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-01-2013

Re: 10G PCS PMA multiple core instance

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Yes, I think so

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