07-01-2020 11:32 AM - edited 07-01-2020 11:34 AM
Is there a Xilinx IP that can interface directly from the FPGA to a 10GBASE-T SFP+ module (such as on the vc707)? I'm finding it difficult to even understand what layer of the OSI model is implemented inside these SFP+ transceivers....is it the entire PHY? (LDPC PCS, PMA, AN) or is it just acting like a glorified ADC/DAC? I'm also finding it difficult to put a name and specification on the interface going to these modules: For the high speed stuff, they only have 1 tx pair and 1 rx pair. What is the data format?
07-01-2020 11:53 AM
I'd take a look at XAPP1305:
And the 10G Subsystem
But as quick simplification:
the Linux TCP/IP stack here implemented levels 4 & 3 of the OSI model. The MAC/10G Subsystem (which contains the MAC and the GT/transceivers for part of the PCS/PMD) implemented level 2 and part of level 1... And an external SFP+ 10G-BaseT module was used as well. The GTs can be used directly to interface to optical modules (e.g. 10GBase-R) or for some FPGA families a backplane (10GBase-KR) but you'll need an external transceiver (inside the SFP+ module here) for Base-T.
07-15-2020 03:27 PM
The 10GBASE-T SFP+ would have an SFI or XFI interface facing the FPGA, accepting 64b/66b encoded data exactly the same as the 10GBASE-R wire format and performing all of the additional encoding and FEC required for 10GBASE-T. You can think of the 10GBASE-T SFP+ as being a protocol converter between 10GBASE-R and 10GBASE-T. From the FPGA point of view, it looks exactly the same as an SFP+ DAC cable or SFP+ optical module.