02-11-2020 02:34 AM
I am using XCZU19EGFFVD1760 FPGA board, and I am checking the 25G Ethernet Speed on Zynq UltraScale+ board with QSFP but GTY transceiver is not working.
In 10G/25G Ethernet Subsytem IP, I have set the GT selection and configuration according to the documents.
What could be the problem ? Anyone can suggest please
Speed : 25G
Enabled : 4 Cores
GT Selection and Configuration : GTY , Clock : 322.265 MHZ.
02-12-2020 07:18 PM
Is this for simulation?
Please try IP core example design first.
And add "-d SIM_SPEED_UP" to speed up the simulation
Can you see data in simulation?
02-12-2020 08:43 PM
>>>>Is this for simulation? NO
After generating bitstream and dupping the .bit file into hardware. Then checking the output in ILA.
02-12-2020 10:24 PM
Still you can try IP core example design with near end loopback mode first.
You can also run IBERT first to confirm that GTY HW environment is good.
02-13-2020 12:39 AM
>>Still you can try IP core example design with near end loopback mode first.
Any link please :(
02-13-2020 03:28 AM
Right click on the IP core .xci file in Vivado project and select "generate IP core example design"
02-13-2020 08:43 PM
Hi @thaus_015 ,
Also, please refer to page 20 for further detail of IBERT example design in https://www.xilinx.com/support/documentation/ip_documentation/ibert_ultrascale_gty/v1_3/pg196-ibert-ultrascale-gty.pdf.