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thaus_015
Explorer
Explorer
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Registered: ‎03-29-2017

40G/50G Ethernet Subsystem (Zynq Ultrascale+)

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I have used Zynq Ultrascale+ to initialise the 40G/50G Ethernet Subsystem IP. If I connect rx_core_clk and rx_clk_out to RX side blocks, its showing clock mismatch error. I have checked rx_reset eventhough facing same problem. 

Gt_ref_clk = 322.2656
rx_clk & tx_clk = 312.5 Mhz

axis_rx.png

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nanz
Moderator
Moderator
247 Views
Registered: ‎08-25-2009

Hi @thaus_015 , 

Please try the latest version if possible to see if the issue still exists. 

This is in IPI, but you may try in the wrapper file to connect the interface as a workaround. 


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Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs and our Versal Ethernet Sticky Note.

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nanz
Moderator
Moderator
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Registered: ‎08-25-2009

Hi @thaus_015 ,

I built a quick test project to reproduce it but it's not reproducible:

nanz_0-1612801466292.png

rx_axis_* interface are in rx_clk_out domain as per PG. 

Which version of the tool are you using? 


-------------------------------------------------------------------------------------------

Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs and our Versal Ethernet Sticky Note.

-------------------------------------------------------------------------------------------
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thaus_015
Explorer
Explorer
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Registered: ‎03-29-2017

No, I am facing same issue. I have attached the design. How to debug please suggest me ?

axis_rx.png

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thaus_015
Explorer
Explorer
267 Views
Registered: ‎03-29-2017

Thanks for your response. 

I am using 2019.1 vivado, and board number ; XCZU19EG-FFVD1760-3E. What you have tried, the same thing i tried. But same error. 

ether.png 

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nanz
Moderator
Moderator
248 Views
Registered: ‎08-25-2009

Hi @thaus_015 , 

Please try the latest version if possible to see if the issue still exists. 

This is in IPI, but you may try in the wrapper file to connect the interface as a workaround. 


-------------------------------------------------------------------------------------------

Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs and our Versal Ethernet Sticky Note.

-------------------------------------------------------------------------------------------

View solution in original post

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